Digital Logic & Microprocessor — Sequential Logic Circuit, NEC licence examination syllabus (Nepal Engineering Council).
Synchronous Counters: every flip-flop clocked together
More logic, more wires — and no glitches at any speed.
An asynchronous counter is slow because the clock ripples. The fix is obvious once stated: give every flip-flop the same clock, and use combinational logic to decide which ones should toggle. Now all stages change simultaneously, no false states appear, and the maximum frequency no longer depends on how many bits you have. The price is the logic you must design — and there's a standard procedure for that.
The toggle rule
For a binary UP counter, a stage toggles when ALL lower
stages are 1:
FF0: always toggles → J₀ = K₀ = 1
FF1: toggles when Q0 = 1 → J₁ = K₁ = Q0
FF2: toggles when Q1·Q0 = 1 → J₂ = K₂ = Q1·Q0
FF3: toggles when Q2·Q1·Q0=1 → J₃ = K₃ = Q2·Q1·Q0
For a DOWN counter, use the complements:
J₁ = K₁ = Q0'
J₂ = K₂ = Q1'·Q0' etc.
Gate count grows, but delay does NOT — all AND gates work
in parallel from the same clock edge.
The five-step design procedure
This works for ANY sequence, not just binary counting:
1. Determine the number of flip-flops: 2ⁿ ≥ number of states
2. Draw the STATE TRANSITION TABLE (present state →
next state)
3. For each flip-flop, use its EXCITATION TABLE to find the
required inputs for every transition
4. K-MAP each flip-flop input as a function of the present
state; simplify
5. Draw the circuit
Worked numerical 1 — a full MOD-8 synchronous up counter
Design a 3-bit synchronous binary up counter using JK flip-flops. Show the complete design procedure.
STEP 1 — 8 states → n = 3 flip-flops (Q2 Q1 Q0)
STEP 2 — state table:
Present Next
Q2 Q1 Q0 | Q2+ Q1+ Q0+
─────────┼─────────────
0 0 0 | 0 0 1
0 0 1 | 0 1 0
0 1 0 | 0 1 1
0 1 1 | 1 0 0
1 0 0 | 1 0 1
1 0 1 | 1 1 0
1 1 0 | 1 1 1
1 1 1 | 0 0 0 (wraps)
STEP 3 — JK excitation for each flip-flop.
Recall: 0→0 needs J=0,K=X; 0→1 needs J=1,K=X;
1→0 needs J=X,K=1; 1→1 needs J=X,K=0
Q2Q1Q0 | J2 K2 | J1 K1 | J0 K0
───────┼───────┼───────┼───────
0 0 0 | 0 X | 0 X | 1 X
0 0 1 | 0 X | 1 X | X 1
0 1 0 | 0 X | X 0 | 1 X
0 1 1 | 1 X | X 1 | X 1
1 0 0 | X 0 | 0 X | 1 X
1 0 1 | X 0 | 1 X | X 1
1 1 0 | X 0 | X 0 | 1 X
1 1 1 | X 1 | X 1 | X 1
STEP 4 — K-map each column:
J0 = 1 (always 1 or X) K0 = 1
J1 = Q0 K1 = Q0
J2 = Q1·Q0 K2 = Q1·Q0
STEP 5 — circuit:
FF0: J=K=1 (tied high)
FF1: J=K=Q0
FF2: J=K= output of an AND gate on Q1,Q0
Total: 3 JK flip-flops + 1 two-input AND gate.
This matches the toggle rule stated above — the formal
procedure confirms the shortcut.
Worked numerical 2 — MOD-5 synchronous counter
Design a synchronous counter for the sequence 0,1,2,3,4,0,… using JK flip-flops.
STEP 1 — 5 states → n = 3 (8 states available; 5,6,7 unused)
STEP 2 — state table (unused states are don't-cares):
Q2 Q1 Q0 | Q2+ Q1+ Q0+
─────────┼─────────────
0 0 0 | 0 0 1
0 0 1 | 0 1 0
0 1 0 | 0 1 1
0 1 1 | 1 0 0
1 0 0 | 0 0 0 ← wraps to 0
1 0 1 | X X X (unused)
1 1 0 | X X X (unused)
1 1 1 | X X X (unused)
STEP 3 — excitation table:
Q2Q1Q0 | J2 K2 | J1 K1 | J0 K0
───────┼───────┼───────┼───────
0 0 0 | 0 X | 0 X | 1 X
0 0 1 | 0 X | 1 X | X 1
0 1 0 | 0 X | X 0 | 1 X
0 1 1 | 1 X | X 1 | X 1
1 0 0 | X 1 | 0 X | 0 X
others | X X | X X | X X
STEP 4 — K-maps (using the don't-cares generously):
J2 = Q1·Q0
K2 = 1
J1 = Q0
K1 = Q0
J0 = Q2' ← this is the key term that forces the
wrap at 4 instead of continuing to 5
K0 = 1
Check J0 = Q2': at state 100 (Q2=1), J0 = 0 so Q0 stays 0,
and K2 = 1 resets Q2 → next state 000 ✔
Total: 3 JK flip-flops + 1 AND gate + 1 inverter.
Verify the full sequence:
000 → J0=1 → 001 ✔
001 → J1=1,K0=1 → 010 ✔
010 → J0=1 → 011 ✔
011 → J2=1,K1=1,K0=1 → 100 ✔
100 → K2=1, J0=0 → 000 ✔ wraps correctly
Worked numerical 3 — async vs sync frequency comparison
Compare maximum frequency for 4-bit and 16-bit counters. Flip-flop delay 10 ns, AND gate delay 6 ns.
ASYNCHRONOUS (ripple):
4-bit: t = 4 × 10 = 40 ns → 25 MHz
16-bit: t = 16 × 10 = 160 ns → 6.25 MHz
SYNCHRONOUS:
The critical path is one flip-flop delay plus the
combinational logic feeding the last stage.
4-bit: t = 10 + 6 = 16 ns → 62.5 MHz
16-bit: with cascaded ANDs, the logic depth grows
slightly (say 2 gate levels for 16 bits):
t = 10 + 12 = 22 ns → 45.5 MHz
Speed advantage of synchronous:
4-bit: 62.5/25 = 2.5×
16-bit: 45.5/6.25 = 7.3×
The wider the counter, the bigger the synchronous advantage.
Hardware cost comparison (4-bit):
async: 4 FFs, 0 gates
sync: 4 FFs, 2 AND gates
Two extra gates for 2.5× the speed and no glitches — which
is why every counter inside a CPU is synchronous.
⚔️ Asynchronous vs Synchronous counters
ClockingAsync: each FF clocked by the previous output. Sync: all FFs share one clock.
SpeedAsync: f_max = 1/(n·t_p) — falls as bits increase. Sync: f_max = 1/(t_p + t_gate) — nearly independent of width.
GlitchesAsync: false intermediate states during ripple. Sync: none — all outputs change together.
HardwareAsync: minimal, no extra gates. Sync: needs AND gates for the toggle logic.
Use whenAsync: simple frequency division where glitches don't matter. Sync: anything driving decoders, or any speed-critical design.
💡 Exam angle: this is the highest-value topic in the section — expect a full 10-mark design question. Follow the five steps explicitly and show the excitation table; that's where most marks sit. Memorise the toggle rule (J_n = K_n = product of all lower Q's) as a check on your K-mapped answer. For MOD-N counters, exploit the unused states as don't-cares — it simplifies the logic substantially.
Syllabus points
Synchronous counter design (numerical)
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