Digital Logic & Microprocessor — Sequential Logic Circuit, NEC licence examination syllabus (Nepal Engineering Council).
Shift Register Applications: rings, Johnsons and serial links
Feed a shift register's output back to its input and it becomes a counter with a very useful property.
A shift register moves data along a chain. Connect the last output back to the first input and the data circulates forever — and suddenly you have a counter whose outputs change one bit at a time. That property matters more than it sounds: it means no glitches, no decoding hazards, and it's why ring counters still appear in real designs despite being less efficient than binary counters.
Ring counter
Feed Q_last back to D_first. Preload exactly ONE 1.
4-bit ring counter sequence:
1000 → 0100 → 0010 → 0001 → 1000 → …
n flip-flops give n states (not 2ⁿ!)
Only ONE output is high at a time.
Advantages:
· No decoding needed — each output IS a state
· Only one bit changes... actually TWO change per step
· Extremely simple
Disadvantage:
· Very inefficient: 4 flip-flops for only 4 states,
when a binary counter would give 16.
Johnson counter (twisted-ring)
Feed Q_last' (the COMPLEMENT) back to D_first.
Start from all zeros.
4-bit Johnson counter sequence:
0000 → 1000 → 1100 → 1110 → 1111
→ 0111 → 0011 → 0001 → 0000 → …
n flip-flops give 2n states — TWICE the ring counter.
4 flip-flops → 8 states.
The key property: exactly ONE bit changes per transition
(it is a Gray-code-like sequence). No glitches possible.
The single-bit-change property of a Johnson counter is why it's used to drive stepper motors and multiplexed displays. When only one bit changes, there is no instant where the outputs pass through a wrong intermediate value — so no decoding glitch, no motor jitter, no display flicker. A binary counter going from 0111 to 1000 changes four bits and can momentarily show any of several wrong values.
Worked numerical 1 — state count comparison
Compare the number of states and flip-flops needed for a 12-state sequencer built three ways.
RING COUNTER:
states = n → need n = 12 flip-flops
Decoding: none (each output is a state)
Total: 12 FFs + 0 gates
JOHNSON COUNTER:
states = 2n → 2n = 12 → n = 6 flip-flops
Decoding: 2-input gates per state (12 gates)
Total: 6 FFs + 12 gates
BINARY COUNTER:
states = 2ⁿ → need 2ⁿ ≥ 12 → n = 4 flip-flops
Decoding: 4-input gates per state (12 gates)
Total: 4 FFs + 12 wider gates + glitch risk
Summary:
Ring: most flip-flops, zero decoding, glitch-free
Johnson: half the ring's flip-flops, simple decoding,
glitch-free
Binary: fewest flip-flops, widest decoding, GLITCHES
Johnson is often the sweet spot for sequencers, which is
exactly why the 4017 Johnson decade counter is a classic
part for LED chasers and stepper drivers.
Worked numerical 2 — serial data transfer timing
Two systems transfer 1 KB of data over a serial link using shift registers at 500 kHz. Find the transfer time, and compare with an 8-bit parallel link at the same clock.
SERIAL:
Data = 1 KB = 1024 bytes = 8192 bits
Clock = 500 kHz → 1 bit per 2 µs
Time = 8192 × 2 µs = 16 384 µs = 16.38 ms
PARALLEL (8 bits at a time):
Transfers needed = 1024 bytes = 1024 clocks
Time = 1024 × 2 µs = 2048 µs = 2.05 ms
Parallel is exactly 8× faster (as expected).
But count the wires:
serial: 2 (data + clock)
parallel: 9 (8 data + clock)
And at high speed parallel suffers from SKEW — the 8 bits
arrive at slightly different times because the traces have
different lengths. Above roughly 100 MHz this becomes the
limiting factor, which is why modern high-speed links
(USB, SATA, PCIe) all went back to serial with very fast
clocks rather than wide parallel buses.
Worked numerical 3 — sequence generator
Design a circuit to generate the repeating sequence 10110 using a shift register with feedback.
Sequence length = 5 bits, so we need a counter with 5 states.
Approach: use a 3-bit shift register (8 possible states) with
feedback logic chosen to produce the pattern.
Simpler approach for exams — use a 5-bit ring counter to
generate 5 timing phases, then OR the phases where the
output should be 1:
Ring states: T0 T1 T2 T3 T4
Desired out: 1 0 1 1 0
Output = T0 + T2 + T3
Cost: 5 flip-flops + one 3-input OR gate.
Alternative with a Johnson counter (3 FFs → 6 states, one
state unused) or a 3-bit binary counter (8 states) plus a
K-mapped output function — fewer flip-flops but needs
decoding gates and risks glitches during transitions.
For a LINEAR FEEDBACK SHIFT REGISTER (LFSR), feedback taps
are XORed to give a maximal-length sequence of 2ⁿ−1 states:
3-bit LFSR → 7 states, used for pseudo-random generation
and CRC error checking.
💡 Exam angle: the ring-versus-Johnson comparison is the standard question — n states versus 2n states, and Johnson's single-bit-change advantage. Write out both sequences fully; they earn marks directly. Mention the glitch-free property and one real application (stepper motor, LED sequencer). LFSRs are a good bonus mention for pseudo-random generation.
Syllabus points
Ring & Johnson counters, data transfer
Create a free account to tick topics off, take notes as you read, watch the video lessons and get a day-by-day study plan built around your exam date.