Digital Logic & Microprocessor — Sequential Logic Circuit, NEC licence examination syllabus (Nepal Engineering Council).
Asynchronous Counters: cheap, simple, and subtly broken
Each flip-flop clocks the next. It works — until you look at the timing closely.
The easiest counter to build: take toggling flip-flops and use each one's output as the clock for the next. Since each stage divides by two, the outputs together count in binary. Two gates of wiring and you're done. But because the clock signal has to ripple down the chain, the stages don't change simultaneously — and during that ripple the counter briefly displays values it should never show.
Construction
Also called a RIPPLE counter.
All flip-flops in toggle mode (J = K = 1, or T = 1)
FF0 clocked by the external clock
FF1 clocked by Q0
FF2 clocked by Q1
FF3 clocked by Q2 … and so on
Each stage divides its input frequency by 2, so:
f(Q0) = f_clk/2
f(Q1) = f_clk/4
f(Q2) = f_clk/8
f(Q3) = f_clk/16
Counting direction depends on which output you tap:
clock the next stage from Q → DOWN counter
clock the next stage from Q' → UP counter
(for negative-edge-triggered flip-flops)
The ripple problem
The false states are the real cost. Going from 7 (0111) to 8 (1000), the counter momentarily shows 6, then 4, then 0. If a decoder is watching for "state 4" to trigger something, it fires spuriously. That's why ripple counters must never drive decoders directly in a system where a false pulse matters — and why synchronous counters exist.
Worked numerical 1 — maximum frequency
A 4-bit ripple counter uses flip-flops with 12 ns propagation delay. Find the maximum reliable clock frequency, and compare with an 8-bit version.
All stages must settle before the next clock edge:
4-bit counter:
t_settle = n × t_p = 4 × 12 = 48 ns
f_max = 1/48 ns = 20.83 MHz
8-bit counter:
t_settle = 8 × 12 = 96 ns
f_max = 1/96 ns = 10.42 MHz
16-bit counter:
t_settle = 16 × 12 = 192 ns
f_max = 5.21 MHz
The frequency limit is INVERSELY PROPORTIONAL to the number
of bits — doubling the width halves the speed. That is the
fundamental flaw of ripple counters.
A synchronous counter of any width runs at:
f_max = 1/(t_p + t_gate)
= 1/(12 + 8) = 50 MHz regardless of width
For a 16-bit counter that's nearly 10× faster.
Worked numerical 2 — designing a MOD-10 (decade) counter
Design an asynchronous MOD-10 counter that counts 0–9 then resets, using JK flip-flops with active-low asynchronous CLEAR.
Number of flip-flops needed:
2ⁿ ≥ 10 → n = 4 (gives 16 states, we use 10)
Method: let it count 0–9 normally, then detect state 10
(1010) and immediately clear all flip-flops.
State 10 in binary = 1010, i.e. Q3=1, Q2=0, Q1=1, Q0=0
Detect it with a NAND on the bits that are 1:
CLEAR' = (Q3 · Q1)'
When Q3=1 AND Q1=1 → CLEAR' goes low → all FFs reset to 0
Why only Q3 and Q1? Because 1010 is the FIRST state in the
0–15 sequence where both Q3 and Q1 are high. Check:
8 = 1000: Q3=1, Q1=0 → no clear ✔
9 = 1001: Q3=1, Q1=0 → no clear ✔
10 = 1010: Q3=1, Q1=1 → CLEAR fires ✔
Sequence: 0,1,2,…,9, (briefly 10), 0, 1, …
CAUTION — the glitch: state 1010 does appear momentarily
before the clear takes effect. This "transient state" is
unavoidable in async MOD-N designs and is another reason
synchronous designs are preferred.
MOD-N general rule:
detect state N, use it to clear
n = ceil(log₂ N) flip-flops
Worked numerical 3 — MOD-6 counter and frequency division
Design a MOD-6 counter and find the output frequency at each stage from a 1.2 MHz clock.
MOD-6: count 0–5, reset on 6.
2ⁿ ≥ 6 → n = 3 flip-flops
State 6 = 110, so Q2=1, Q1=1, Q0=0
CLEAR' = (Q2 · Q1)'
Sequence: 000,001,010,011,100,101,(110→clear),000,…
0 1 2 3 4 5
Output frequencies:
Q0 toggles every clock: 1.2 MHz / 2 = 600 kHz
Q1 toggles every 2 clocks: 600 / 2 = 300 kHz
Q2 — but the counter resets at 6, not 8!
For a MOD-N counter the LAST stage output frequency is:
f_out = f_clk / N = 1.2 MHz / 6 = 200 kHz
That divide-by-N property is the main practical use of
MOD-N counters — a MOD-6 divides by 6 exactly.
Verify: in 6 clock cycles Q2 completes one full cycle
(low for states 0–3, high for 4–5)
Hmm — 4 low, 2 high: not a 50% duty cycle.
The frequency is right (200 kHz) but the waveform is
asymmetric. Symmetric division needs extra logic.
💡 Exam angle: draw the ripple chain and show the false-state table for one transition (7→8 is the classic) — that's the marks for "why is async counting a problem". For MOD-N design, state n = ceil(log₂ N), give the NAND detect equation on the bits that are 1 in state N, and mention the unavoidable transient state. The f_max = 1/(n × t_p) formula is a guaranteed numerical.
Syllabus points
Ripple counters; mod-N (design)
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