Digital Logic & Microprocessor — Sequential Logic Circuit, NEC licence examination syllabus (Nepal Engineering Council).
Gated Flip-Flops: adding a clock so changes happen when you say
An SR latch reacts instantly. That's the problem — a circuit needs discipline.
A plain SR latch responds the moment its inputs move. In a system with dozens of latches whose inputs come from each other through gates of varying delay, that instant response means chaos: signals ripple through at different times and the machine ends up in a state nobody designed. The fix is a gate — an enable line that decides when the latch is allowed to listen.
The three delays add. Setup time is easy to forget because nothing visibly happens during it — but the data must be STABLE before the edge, not merely arrive by it, so it counts against the period just as much as gate delay does.
Add two AND gates in front of an SR latch:
S_internal = S · EN
R_internal = R · EN
EN = 0 → both internal inputs are 0 → latch HOLDS
(inputs are ignored entirely)
EN = 1 → latch behaves exactly like a normal SR latch
(transparent — output follows input)
This is LEVEL-TRIGGERED (or "level-sensitive"): the latch
listens the whole time EN is high, not at one instant.
The D latch — eliminating the forbidden state
Take a gated SR latch and derive R from S with an inverter:
S = D, R = D'
Now S and R can NEVER both be 1 — the forbidden state is
structurally impossible.
EN D | Q(next)
──────┼──────────
0 X | Q (hold — D ignored)
1 0 | 0
1 1 | 1 (Q follows D)
Characteristic equation: Q(next) = D (when enabled)
"D" stands for Data or Delay. It's the simplest useful
storage element, and the basis of all registers and RAM.
The D latch solves the SR latch's fatal flaw not by adding rules but by making the illegal input unreachable. That's a design principle worth noticing: rather than documenting "don't do this", change the structure so it can't happen. Every register in every CPU is built from D-type storage for exactly this reason.
The remaining problem: transparency
⚠️ Three problems with level-triggering
TransparencyWhile EN is high, the output tracks the input continuously. If D wobbles three times during the enable window, Q wobbles three times too. You wanted one value, you got a live wire.
Race-throughCascade two latches sharing one EN and data flows straight through both while EN is high — so a shift register won't shift, it'll just pass the value along the whole chain in one clock.
Race-around (SR/JK)With a gated JK latch in toggle mode (J=K=1), the output flips, feeds back, flips again — oscillating for as long as EN stays high.
Worked numerical 1 — race-through in a shift register
Two gated D latches are cascaded (Q₁ → D₂) sharing one enable. Initially Q₁=0, Q₂=0. Set D₁=1 and raise EN. What happens?
Latch 1 propagation delay: 5 ns
Latch 2 propagation delay: 5 ns
EN pulse width: 50 ns
t=0 EN goes high, D₁ = 1
t=5ns Latch 1 becomes transparent → Q₁ = 1
t=10ns Latch 2 sees D₂ = 1, also transparent → Q₂ = 1
By t=10 ns BOTH latches hold 1 — but EN is high until 50 ns.
What we WANTED: Q₁=1, Q₂=0 (the old Q₁ value shifted in)
What we GOT: Q₁=1, Q₂=1 (the data raced through)
The shift register doesn't shift. With four latches, the
value would race through all four in 20 ns.
FIX: edge triggering. If each latch samples only at the
instant of the clock edge, latch 2 captures Q₁'s OLD value
before latch 1 has a chance to change it.
Required EN pulse width for correct level-triggered
operation: less than 5 ns — impractically narrow, and
unreliable across temperature and voltage.
Worked numerical 2 — setup and hold times
A D latch has setup time 3 ns, hold time 2 ns, and propagation delay 6 ns. Data changes 2 ns before the enable falls. Is the capture reliable?
SETUP TIME (t_su): data must be STABLE for this long
BEFORE the enable edge.
HOLD TIME (t_h): data must remain stable for this long
AFTER the edge.
Given: data changed only 2 ns before the edge.
Required setup: 3 ns
2 ns < 3 ns → SETUP VIOLATION ✗
Consequence: the latch may capture the old value, the new
value, or enter a METASTABLE state — hovering between 0
and 1 for an unpredictable time before settling randomly.
Metastability is the reason asynchronous inputs (a button,
data from another clock domain) must be synchronised through
two flip-flops before use.
Maximum safe clock frequency for a chain of such latches:
T_min = t_prop + t_logic + t_su
If combinational logic between stages takes 10 ns:
T_min = 6 + 10 + 3 = 19 ns → f_max = 52.6 MHz
💡 Exam angle: define level-triggered versus edge-triggered clearly and explain the three problems (transparency, race-through, race-around) — that's what motivates every later flip-flop. The D latch's key point is that S = D, R = D' makes the forbidden state structurally impossible. Setup and hold times appear in "maximum clock frequency" numericals.
Syllabus points
Clocked/gated flip-flops
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