Digital Logic & Microprocessor — Sequential Logic Circuit, NEC licence examination syllabus (Nepal Engineering Council).
Edge-Triggered Flip-Flops: sampling at one instant
Not "while the clock is high" but "at the moment the clock rises". That changes everything.
A level-triggered latch listens for the whole time its enable is high, and we saw the trouble that causes. An edge-triggered flip-flop listens for a vanishingly short window at the clock transition — it takes one sample and then ignores its input until the next edge. That single change makes synchronous design possible, which is why every processor, every register and every counter you will ever meet is edge-triggered.
D flip-flop
CLK D | Q(next)
────────┼──────────
↑ 0 | 0
↑ 1 | 1
0/1 X | Q (holds between edges)
Characteristic equation: Q(next) = D
The simplest and most used flip-flop. One data input,
captured once per clock edge. Every register is a row of
these sharing one clock.
JK flip-flop — the versatile one
J K | Q(next) | Action
─────┼──────────┼──────────
0 0 | Q | Hold
0 1 | 0 | Reset
1 0 | 1 | Set
1 1 | Q' | TOGGLE ← the useful extra
Characteristic equation:
Q(next) = JQ' + K'Q
The JK fixes the SR latch's forbidden state by turning it
into something genuinely useful: toggle. That is what makes
counters possible.
T flip-flop
T | Q(next) | Action
───┼──────────┼─────────
0 | Q | Hold
1 | Q' | Toggle
Characteristic equation:
Q(next) = T ⊕ Q
Built from a JK with J and K tied together (T = J = K),
or from a D flip-flop with D = T ⊕ Q.
Used for frequency division and ripple counters.
Look at the two Q traces. The level-triggered output copies every wiggle of D during the high phase; the edge-triggered output changes exactly three times, once per clock edge. That predictability is the entire foundation of synchronous digital design — you can reason about the circuit one clock cycle at a time.
All four excitation tables
The design tables — "I want this transition, what input?"
Q → Q(next) | SR | D | JK | T
────────────┼──────┼─────┼──────┼────
0 → 0 | 0 X | 0 | 0 X | 0
0 → 1 | 1 0 | 1 | 1 X | 1
1 → 0 | 0 1 | 0 | X 1 | 1
1 → 1 | X 0 | 1 | X 0 | 0
Count the don't-cares:
D: none — simplest to understand, most logic needed
SR: four
JK: FOUR (one per row) — most design freedom
T: none — but trivial for counters
JK's don't-cares usually give the simplest counter logic,
which is why exam questions favour JK for counter design.
Worked numerical 1 — tracing a JK flip-flop
A JK flip-flop starts at Q=0. Trace Q for the input sequence (J,K) = (1,0), (0,0), (1,1), (1,1), (0,1), (1,1) on successive clock edges.
Edge | J K | Action | Q before | Q after
─────┼─────┼─────────┼──────────┼─────────
init | | | | 0
1 | 1 0 | SET | 0 | 1
2 | 0 0 | HOLD | 1 | 1
3 | 1 1 | TOGGLE | 1 | 0
4 | 1 1 | TOGGLE | 0 | 1
5 | 0 1 | RESET | 1 | 0
6 | 1 1 | TOGGLE | 0 | 1
Verify with the characteristic equation Q(next) = JQ' + K'Q:
Edge 3: J=1,K=1,Q=1 → (1)(0) + (0)(1) = 0 ✔
Edge 4: J=1,K=1,Q=0 → (1)(1) + (0)(0) = 1 ✔
Edge 2: J=0,K=0,Q=1 → (0)(0) + (1)(1) = 1 ✔ (hold)
Note edges 3, 4 and 6 all had J=K=1 but produced different
outputs — because toggle depends on the CURRENT state, not
just the inputs. That state dependence is what makes this
sequential rather than combinational.
Worked numerical 2 — converting between flip-flop types
Convert a D flip-flop into a JK flip-flop, and a JK into a T.
D → JK:
We need D to produce the JK behaviour, so set
D = Q(next) = JQ' + K'Q
Circuit: two AND gates and an OR gate feeding D, with Q
and Q' fed back from the output.
Cost: 3 gates + the flip-flop.
JK → T:
T flip-flop: Q(next) = T ⊕ Q
JK toggles when J=K=1 and holds when J=K=0.
So simply tie J = K = T.
Cost: a wire. No gates at all.
D → T:
D = Q(next) = T ⊕ Q
Cost: one XOR gate.
JK → D:
D behaviour: Q(next) = D
Set J = D and K = D'
Cost: one inverter.
General method for any conversion:
1. Write the target flip-flop's excitation table.
2. Beside it, write the source flip-flop's required inputs.
3. K-map each source input against the target inputs and Q.
4. Build that logic.
Worked numerical 3 — maximum clock frequency
A D flip-flop has propagation delay 8 ns, setup time 4 ns, hold time 2 ns. Between two flip-flops sits combinational logic with 12 ns delay. Find the maximum clock frequency.
The data must leave FF1, cross the logic, and be stable at
FF2's input before FF2's setup window opens:
T_clk(min) = t_prop(FF1) + t_logic + t_setup(FF2)
= 8 + 12 + 4
= 24 ns
f_max = 1/24 ns = 41.67 MHz
Hold-time check — the data must NOT arrive too early:
t_prop + t_logic ≥ t_hold
8 + 12 = 20 ns ≥ 2 ns ✔ satisfied comfortably
If we removed the combinational logic entirely:
T_min = 8 + 0 + 4 = 12 ns → f_max = 83.3 MHz
Hold check: 8 ≥ 2 ✔ still fine
Notice the logic delay dominates. This is why CPU designers
break long combinational paths into pipeline stages — each
stage's logic delay shrinks, so the clock can run faster.
💡 Exam angle: memorise all four characteristic equations (D=Q_next, JK: JQ'+K'Q, T: T⊕Q) and the combined excitation table — both are frequently asked directly. Flip-flop conversion is a standard 5–6 mark question; use the four-step method. The maximum-frequency formula T = t_prop + t_logic + t_setup appears in nearly every paper.
Syllabus points
D, JK, T edge-triggered flip-flops
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