Digital Logic & Microprocessor — Sequential Logic Circuit, NEC licence examination syllabus (Nepal Engineering Council).
Master-Slave Flip-Flops: two latches, one clock, no race
The clever fix that made edge triggering possible before anyone had fast edge detectors.
A gated JK latch in toggle mode oscillates: the output flips, feeds back, flips again, and keeps going for as long as the clock is high. This is the race-around condition, and it makes level-triggered JK latches useless. The master-slave arrangement fixes it with a genuinely elegant idea — use two latches driven by opposite clock phases, so only one is ever listening.
The race-around problem, quantified
A gated JK latch with J = K = 1 (toggle mode):
Propagation delay of the latch: t_p
Clock high duration: t_pw (pulse width)
If t_pw > t_p, the output toggles, the new value feeds back,
and it toggles AGAIN — repeatedly, for as long as the clock
stays high.
Number of unwanted toggles ≈ t_pw / t_p
The final state depends on whether that count is odd or
even — which depends on temperature, supply voltage and
manufacturing spread. Completely unusable.
The "solution" of making t_pw < t_p requires a pulse
narrower than a gate delay: impractical.
How master-slave works
Two gated latches in series with INVERTED clocks:
MASTER: enabled when CLK = 1
SLAVE: enabled when CLK = 0 (clock inverted)
Timeline for one clock cycle:
CLK goes HIGH:
Master becomes transparent, captures J,K
Slave is DISABLED — holds its old value
→ the output Q does NOT change, so no feedback race
CLK goes LOW:
Master is DISABLED — freezes what it captured
Slave becomes transparent, copies the master
→ Q changes ONCE, at the falling edge
Result: exactly one output change per clock cycle,
occurring on the negative edge. Race-around eliminated,
because master and slave are NEVER transparent together.
The reason master-slave defeats race-around: at every instant, exactly one of the two latches is transparent. There is never a complete path from the output back to the input while that input is being sampled, so the feedback loop can't run away. The output can only change when the master is already frozen.
Worked numerical 1 — counting the race-around toggles
A gated JK latch has a propagation delay of 15 ns and is clocked with a 100 ns high pulse, with J=K=1. How many times does the output toggle, and what is the final state if Q started at 0?
Toggles during the high phase:
n = t_pw / t_p = 100/15 = 6.67 → about 6 toggles
Starting from Q = 0, after 6 toggles: Q = 0
(even number of toggles returns to the start)
But 6.67 is not an integer, so whether the 7th toggle
completes depends on exact timing. With 7 toggles: Q = 1.
The output is therefore UNPREDICTABLE — the answer depends
on whether t_p is 14 ns or 16 ns on the day.
For correct level-triggered operation we would need:
t_pw < t_p → pulse narrower than 15 ns
At a 50% duty cycle that means a clock period under 30 ns,
i.e. above 33 MHz — and even then it is marginal.
Master-slave removes the constraint entirely: the pulse
width no longer matters at all.
Worked numerical 2 — the "1s catching" flaw
A master-slave JK has J=0, K=0 when the clock goes high, but a brief noise glitch sets J=1 momentarily before the clock falls. What happens?
Timeline:
CLK high, J=K=0 → master holds its current value
glitch: J = 1 briefly → master (transparent!) captures
the SET condition
glitch ends, J back to 0 → master has ALREADY latched 1
CLK falls → slave copies the master → Q = 1
The flip-flop responded to a glitch that had vanished long
before the clock edge. This is called ONES CATCHING (or
zeros catching for K).
Why it happens: the master is transparent for the whole
high phase, so it is vulnerable the whole time.
FIX: true edge-triggered designs, which use an edge-detector
circuit (a short pulse generated from the clock transition
itself) so the sampling window is only a few nanoseconds
wide. Modern flip-flops are edge-triggered, not master-slave,
largely for this reason.
Worked numerical 3 — frequency division
A master-slave JK with J=K=1 is clocked at 8 MHz. What is the output frequency, and what if four such stages are cascaded?
With J=K=1 the flip-flop toggles once per clock edge
(the falling edge for master-slave).
Q changes state every input cycle
→ two input cycles produce one full output cycle
→ f_out = f_in / 2 = 8/2 = 4 MHz
This is a divide-by-2 circuit — the basic frequency divider.
Cascading four stages (each output clocking the next):
Stage 1: 8 MHz → 4 MHz
Stage 2: 4 MHz → 2 MHz
Stage 3: 2 MHz → 1 MHz
Stage 4: 1 MHz → 0.5 MHz
f_out = f_in/2⁴ = 8/16 = 0.5 MHz
General: n toggling flip-flops divide by 2ⁿ.
And the four outputs taken together count 0,1,2,…,15 in
binary — which is exactly a 4-bit ripple counter, the
subject of the next topic.
💡 Exam angle: define the race-around condition and state its cause (t_pw > t_p in toggle mode) — then explain the master-slave fix in terms of the two latches never being transparent simultaneously. Mention that master-slave triggers on the falling edge and that it still suffers from 1s-catching, which true edge triggering solves. The divide-by-2ⁿ result is worth stating.
Syllabus points
Master-slave operation; race-around
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