Digital Logic & Microprocessor — Sequential Logic Circuit, NEC licence examination syllabus (Nepal Engineering Council).
The SR Latch: the first circuit that can remember
Two NOR gates staring at each other. That's all memory is at the bottom.
Everything so far has been combinational — output depends only on the present input. But a computer needs to remember. The trick that makes memory possible is startlingly simple: take two NOR gates and feed each one's output back into the other's input. The pair now has two stable states it can sit in indefinitely, and which one it's in depends on what happened earlier. That's storage.
How the feedback creates memory
Cross-coupled NOR gates:
Q = (R + Q')'
Q' = (S + Q)'
Case S=0, R=0 (both inactive):
Whatever Q currently is, the feedback holds it there.
→ HOLD / memory state
Case S=1, R=0:
Q' is forced to 0, which frees Q to become 1.
→ SET (Q = 1)
Case S=0, R=1:
Q is forced to 0, Q' becomes 1.
→ RESET (Q = 0)
Case S=1, R=1:
Both outputs forced to 0 — but Q and Q' should be
complements! → FORBIDDEN / INVALID
Truth table (NOR-based SR latch, active HIGH inputs):
S R | Q(next) | State
─────┼───────────┼──────────
0 0 | Q | Hold (remembers)
0 1 | 0 | Reset
1 0 | 1 | Set
1 1 | — | INVALID (Q = Q' = 0)
Why S=R=1 is genuinely dangerous, not merely "undefined": when you release both inputs simultaneously, the two gates race to grab the output, and which one wins depends on microscopic differences in propagation delay. The result is unpredictable and can differ between two identical chips. This one flaw is what every later flip-flop design exists to fix.
NAND-based version — active LOW
Cross-coupled NAND gates give an S'R' latch with
ACTIVE-LOW inputs:
S' R' | Q(next) | State
───────┼─────────┼──────────
1 1 | Q | Hold
1 0 | 0 | Reset
0 1 | 1 | Set
0 0 | — | INVALID (Q = Q' = 1)
Note everything is inverted: the forbidden state is now
both inputs LOW, and it forces both outputs HIGH.
The NAND version is more common in real ICs.
Characteristic and excitation tables
CHARACTERISTIC TABLE — "given the inputs, what happens?"
Used for ANALYSIS.
S R Q | Q(next)
────────┼─────────
0 0 0 | 0 (hold)
0 0 1 | 1 (hold)
0 1 0 | 0 (reset)
0 1 1 | 0 (reset)
1 0 0 | 1 (set)
1 0 1 | 1 (set)
1 1 0 | X (invalid)
1 1 1 | X (invalid)
Characteristic EQUATION:
Q(next) = S + R'Q with constraint SR = 0
EXCITATION TABLE — "I want this transition, what inputs?"
Used for DESIGN (counters, state machines).
Q → Q(next) | S R
────────────┼────────
0 → 0 | 0 X
0 → 1 | 1 0
1 → 0 | 0 1
1 → 1 | X 0
Worked numerical 1 — tracing a waveform
An SR latch starts with Q=0. Trace Q through this input sequence: (S,R) = (0,0), (1,0), (0,0), (0,1), (0,0), (1,1).
Step | S R | Action | Q
─────┼─────┼───────────────┼────────────────
init | | | 0
1 | 0 0 | hold | 0
2 | 1 0 | SET | 1
3 | 0 0 | hold | 1 ← remembers!
4 | 0 1 | RESET | 0
5 | 0 0 | hold | 0 ← remembers!
6 | 1 1 | INVALID | Q = Q' = 0 (illegal)
Steps 3 and 5 are the point of the whole circuit: with both
inputs inactive, the latch retains what it was last told.
That retention IS memory.
Step 6 breaks the invariant Q = Q'. If the inputs then
return to (0,0), the final state is unpredictable.
Worked numerical 2 — using the excitation table
An SR flip-flop must go from Q=1 to Q=0, then from Q=0 to Q=0. What inputs are needed?
Transition 1 → 0:
From the excitation table: S = 0, R = 1
(must actively reset)
Transition 0 → 0:
From the table: S = 0, R = X (don't care)
Either R=0 (hold at 0) or R=1 (reset to 0) works.
The don't-cares are valuable — in counter design they give
freedom when K-mapping the input equations, which usually
yields simpler logic.
Full excitation table again, note the X positions:
0→0: S=0, R=X
0→1: S=1, R=0
1→0: S=0, R=1
1→1: S=X, R=0
Four transitions, four don't-cares. Compare the JK flip-flop
later, which has even more (two per transition) and is
therefore easiest to design with.
Worked numerical 3 — switch debouncing, a real use
A mechanical switch bounces for about 5 ms when pressed, producing multiple false transitions. Show how an SR latch fixes this.
Problem: a single-pole double-throw (SPDT) switch bouncing
between contacts produces a burst of pulses. A counter
driven by it would count 5 or 6 presses instead of one.
Solution — NAND SR latch with the switch across S' and R':
Switch at position A → S' = 0, R' = 1 → Q = 1
Switch in transit → both S' and R' = 1 → HOLD
Switch at position B → S' = 1, R' = 0 → Q = 0
The key insight: while the contact is in mid-air, BOTH
inputs are inactive, so the latch holds its last value.
Bouncing on the destination contact just re-asserts the
same state repeatedly — which changes nothing.
Result: one clean transition per press, regardless of how
many times the metal bounces. No timers, no software delay,
two gates.
💡 Exam angle: draw the cross-coupled NOR circuit and give the truth table with the four states named (hold, set, reset, invalid) — that's the core 4–5 marks. Explain why S=R=1 is forbidden in terms of the race condition, not just "it's undefined". Know both the characteristic table (for analysis) and the excitation table (for design); papers ask for either by name.
Syllabus points
SR latch; characteristic & excitation table
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