Binary Subtraction

Digital Logic & Microprocessor — Combinational and Arithmetic Circuits, NEC licence examination syllabus (Nepal Engineering Council).

Binary Subtraction: why hardware never actually subtracts

Complement the second number, add one, then use the adder you already built.

You could build a subtractor circuit — half subtractor, full subtractor, borrow logic. Exams ask for it, so you should know it. But almost no real hardware does this, because there's a trick: in two's complement, A − B is just A + (−B), and negating a number is cheap. So the same adder handles both operations, saving half the silicon.

Half subtractor

A B | Diff Borrow ─────┼─────────────── 0 0 | 0 0 0 1 | 1 1 ← 0−1 needs a borrow 1 0 | 1 0 1 1 | 0 0 Difference = A ⊕ B (same as half adder's Sum!) Borrow = A' · B (differs from Carry = A·B)

Full subtractor

A B Bin | Diff Bout ──────────┼───────────── 0 0 0 | 0 0 0 0 1 | 1 1 0 1 0 | 1 1 0 1 1 | 0 1 1 0 0 | 1 0 1 0 1 | 0 0 1 1 0 | 0 0 1 1 1 | 1 1 Diff = A ⊕ B ⊕ Bin (identical to full adder) Bout = A'B + Bin(A ⊕ B)' = A'B + A'Bin + B·Bin

Compare the two circuits: the Difference expression is identical to the Sum expression (A ⊕ B ⊕ Cin). Only the borrow/carry logic differs, and even that differs by just a complement — Borrow uses A'B where Carry uses AB. One XOR gate on the B input converts an adder into a subtractor, which is the entire basis of the combined adder/subtractor circuit.

Two's complement — the practical method

To find the two's complement of B: 1. Invert every bit (one's complement) 2. Add 1 Shortcut: copy bits from the right up to and including the first 1, then invert everything to the left of it. Example: 0101100 → 1010100 (copy "100", invert "0101" to "1010") Then: A − B = A + (two's complement of B) Discard any carry out of the MSB.

Worked numerical 1 — subtraction by two's complement

Compute 1010₂ − 0111₂ (10 − 7) using two's complement in 4 bits.

B = 0111 (7) Two's complement of B: one's complement: 1000 add 1: 1001 (this represents −7) Now ADD: 1010 (10) + 1001 (−7) ─────── 1 0011 Discard the carry out of the MSB: Result = 0011 = 3 ✔ (10 − 7 = 3) The carry-out being 1 indicates NO borrow was needed, i.e. the result is positive. That's the convention: carry-out = 1 → result positive (A ≥ B) carry-out = 0 → result negative (A < B)

Worked numerical 2 — when the answer is negative

Compute 0011₂ − 1010₂ (3 − 10) in 4 bits.

B = 1010 (10) Two's complement: 0101 + 1 = 0110 (represents −10) 0011 (3) + 0110 (−10) ─────── 1001 No carry out of the MSB → the result is NEGATIVE. To read the magnitude, take the two's complement again: 1001 → one's complement 0110 → +1 → 0111 = 7 So the answer is −7 ✔ (3 − 10 = −7) This "complement the result to read it" step is what trips students up. The rule: if carry-out = 0, the result is negative and stored in two's complement form.

Worked numerical 3 — the adder/subtractor circuit

Design one 4-bit circuit that adds when M=0 and subtracts when M=1, using four full adders and four XOR gates.

Wiring: Each B_i goes through an XOR with M: B_i ⊕ M M also feeds the initial carry-in C₀ Case M = 0 (ADD): B_i ⊕ 0 = B_i (unchanged) C₀ = 0 Result = A + B ✔ Case M = 1 (SUBTRACT): B_i ⊕ 1 = B_i' (inverted → one's complement) C₀ = 1 (the "+1" of two's complement) Result = A + B' + 1 = A + (two's comp of B) = A − B ✔ Verify with A=1100 (12), B=0101 (5), M=1: B ⊕ 1111 = 1010 1100 + 1010 + 1 (C₀) ─────── 1 0111 Discard carry → 0111 = 7 ✔ (12 − 5 = 7) Hardware cost: 4 full adders + 4 XOR gates. Compare separate adder AND subtractor: 8 full-adder-sized blocks. The XOR trick halves the silicon — which is why every ALU is built this way.

Worked numerical 4 — one's vs two's complement ranges

Compare the 4-bit ranges and show why two's complement is preferred.

SIGNED MAGNITUDE (MSB = sign): range −7 to +7 Problem: TWO zeros (0000 = +0, 1000 = −0) ONE'S COMPLEMENT: range −7 to +7 Problem: still two zeros (0000 and 1111) Also needs "end-around carry" — add the carry-out back in TWO'S COMPLEMENT: range −8 to +7 ← one extra negative value Only ONE zero (0000) No end-around carry — just discard the carry-out Same adder works for signed and unsigned Range formula for n bits, two's complement: −2ⁿ⁻¹ to +(2ⁿ⁻¹ − 1) 8-bit: −128 to +127 16-bit: −32768 to +32767 Two's complement wins on all three counts: one zero, simpler hardware, one extra number. That's why every processor uses it.

💡 Exam angle: derive both subtractor truth tables and note that Difference = Sum while Borrow uses A'B instead of AB. The highest-value answer is the combined adder/subtractor: explain that B ⊕ M inverts when M=1 and that M also supplies the +1 as C₀. For numericals, always state the carry-out interpretation (1 = positive result, 0 = negative and stored in complement form).

Syllabus points

Half & full subtractor; 2's complement subtraction

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