Demultiplexers

Digital Logic & Microprocessor — Combinational and Arithmetic Circuits, NEC licence examination syllabus (Nepal Engineering Council).

Demultiplexers: one input, many destinations

Exactly a multiplexer running backwards — and almost the same chip as a decoder.

A MUX funnels many inputs into one line. A DEMUX does the reverse: it takes a single input and routes it to one of 2ⁿ outputs, chosen by the select lines. Together they make a complete communication link — MUX at the sending end to share a channel, DEMUX at the receiving end to separate the traffic again.

Operation

A 1-to-2ⁿ DEMUX has: 1 data input (D) n select lines 2ⁿ outputs (Y₀ … Y₂ⁿ₋₁) The selected output receives D; all others sit at 0. 1-to-4 DEMUX equations: Y₀ = S₁'S₀'D Y₁ = S₁'S₀D Y₂ = S₁S₀'D Y₃ = S₁S₀D Truth table: S₁ S₀ | Y₀ Y₁ Y₂ Y₃ ──────┼────────────── 0 0 | D 0 0 0 0 1 | 0 D 0 0 1 0 | 0 0 D 0 1 1 | 0 0 0 D

DEMUX versus decoder — the crucial distinction

⚔️ They look identical. They aren't.

Decodern inputs, 2ⁿ outputs. Exactly one output is asserted, determined purely by the input code. There is no data input — the enable pin, if present, just switches everything off.

DEMUX1 data input, n selects, 2ⁿ outputs. The selected output follows the data input, so it can be 0 or 1 depending on D.

The trickTake a decoder with an enable pin and feed your data into the enable. Now the selected output follows the data — you have a DEMUX. This is why one chip (like the 74138) is sold as both.

The exam question is usually "differentiate decoder and demultiplexer". The sharp answer: a decoder's outputs depend only on the select code, while a demultiplexer's selected output carries the data input. Physically the same circuit — a decoder is a DEMUX with its data input tied permanently to 1.

Worked numerical 1 — DEMUX as a function generator

Implement F(A,B,C) = Σm(1,4,6,7) using a 1-to-8 DEMUX and one OR gate.

Put A,B,C on the select lines and tie D = 1 (so the selected output goes HIGH). With D = 1, output Y_i is HIGH exactly when the select code equals i — i.e. Y_i = m_i. So simply OR together the outputs matching the minterms: F = Y₁ + Y₄ + Y₆ + Y₇ Wiring: one 1:8 DEMUX (or a 3-to-8 decoder), one 4-input OR. Note how convenient this is when you need SEVERAL functions of the same variables: one decoder serves all of them, each with its own OR gate. That's exactly how a CPU's instruction decoder drives many control lines from one opcode. If the decoder has ACTIVE-LOW outputs (common in real chips like the 74138), use a NAND gate instead of the OR: F = (Y₁'·Y₄'·Y₆'·Y₇')'

Worked numerical 2 — MUX–DEMUX communication link

Four sensors must share one wire to a remote receiver. Design the link and find the required channel speed if each sensor is sampled at 1 kHz.

TRANSMITTER: 4-to-1 MUX 4 sensor inputs, 2 select lines from a counter, 1 output onto the shared wire. RECEIVER: 1-to-4 DEMUX 1 input from the wire, the SAME 2 select lines (must stay synchronised!), 4 outputs to the 4 destinations. Channel data rate: each sensor sampled 1000 times per second 4 sensors → 4000 samples per second on the wire → the shared channel must run at 4 kHz minimum Select-line counter frequency: 4 kHz (cycling 00→01→10→11) The critical requirement is SYNCHRONISATION — if the receiver's counter drifts one step, every sensor's data lands at the wrong destination. Real systems send a frame sync pulse to keep the two ends aligned. This is TIME-DIVISION MULTIPLEXING, and it's how a single telephone trunk carries hundreds of calls.

Worked numerical 3 — expanding a DEMUX

Build a 1-to-16 DEMUX from 1-to-4 DEMUXes.

STAGE 1 — one 1:4 DEMUX driven by the HIGH selects S₃S₂. Its four outputs become ENABLE signals. STAGE 2 — four 1:4 DEMUXes, each fed by one stage-1 output as its data input, all sharing the LOW selects S₁S₀. Total: 1 + 4 = 5 DEMUXes Trace an example: S₃S₂S₁S₀ = 1011 (decimal 11) Stage 1: S₃S₂ = 10 → activates its output 2, which enables the third stage-2 DEMUX Stage 2: S₁S₀ = 11 → that DEMUX's output 3 goes active Overall: output (2 × 4) + 3 = 11 ✔ Same tree structure as MUX expansion, and the same 2-stage propagation delay.

💡 Exam angle: the decoder-versus-DEMUX distinction is the most likely 2–4 mark question — answer it with "a decoder's output depends only on the code; a DEMUX's selected output carries the data input, and a decoder is a DEMUX with data tied to 1". For circuit questions, remember real decoder chips have active-low outputs, so use NAND rather than OR when combining them.

Syllabus points

DEMUX operation

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