Digital Logic & Microprocessor — Combinational and Arithmetic Circuits, NEC licence examination syllabus (Nepal Engineering Council).
Multiplexers: a data selector, and secretly a universal logic block
Many inputs, one output, and select lines that decide which gets through.
A multiplexer is a digital rotary switch: 2ⁿ data inputs, n select lines, and one output that carries whichever input the select code points at. That sounds narrow, but there's a second use that makes MUXes genuinely important — you can implement any Boolean function with one, by wiring the truth table's output column straight to the data inputs.
The basic operation
A 2ⁿ-to-1 MUX has:
2ⁿ data inputs (D₀ … D₂ⁿ₋₁)
n select lines (S₀ … Sₙ₋₁)
1 output (Y)
often an ENABLE input (active low)
4-to-1 MUX Boolean expression:
Y = S₁'S₀'D₀ + S₁'S₀D₁ + S₁S₀'D₂ + S₁S₀D₃
Each product term is a minterm of the select lines ANDed
with its data input. That structure is exactly why a MUX
can implement any function.
The universal-logic trick: to implement any n-variable function, take a 2ⁿ-to-1 MUX, put the n variables on the select lines, and connect each data input to the corresponding row of the truth table's output column — a hard 0 or 1. No gates at all, no simplification needed, and it works for every function of that many variables.
Worked numerical 1 — function with an 8:1 MUX
Implement F(A,B,C) = Σm(0,2,3,5,7) using an 8-to-1 multiplexer.
Put A on S₂, B on S₁, C on S₀. Then data input D_i must
equal the function's value for minterm i:
m₀ = 0 in the list? YES → D₀ = 1
m₁ → not listed → D₁ = 0
m₂ → listed → D₂ = 1
m₃ → listed → D₃ = 1
m₄ → not listed → D₄ = 0
m₅ → listed → D₅ = 1
m₆ → not listed → D₆ = 0
m₇ → listed → D₇ = 1
Wiring: D₀,D₂,D₃,D₅,D₇ → logic 1 (V_CC)
D₁,D₄,D₆ → logic 0 (ground)
Gate count: ZERO extra gates. One MUX chip does everything.
Compare a gate implementation of the minimal SOP: you'd
first have to K-map it, then build 3–4 AND gates and an OR.
The MUX version needs no simplification at all.
Worked numerical 2 — using a smaller MUX (the halving trick)
Implement the same F(A,B,C) = Σm(0,2,3,5,7) using only a 4-to-1 MUX.
Put A and B on the select lines; C becomes a DATA input.
Pair the minterms two at a time:
S₁S₀ = AB = 00 → rows m₀ (C=0) and m₁ (C=1)
F: m₀=1, m₁=0 → F = C' → D₀ = C'
S₁S₀ = AB = 01 → rows m₂ (C=0) and m₃ (C=1)
F: m₂=1, m₃=1 → F = 1 → D₁ = 1
S₁S₀ = AB = 10 → rows m₄ (C=0) and m₅ (C=1)
F: m₄=0, m₅=1 → F = C → D₂ = C
S₁S₀ = AB = 11 → rows m₆ (C=0) and m₇ (C=1)
F: m₆=0, m₇=1 → F = C → D₃ = C
Wiring: D₀ = C', D₁ = 1, D₂ = C, D₃ = C
Cost: one 4:1 MUX + one inverter (for C').
The general rule: an n-variable function needs only a
2ⁿ⁻¹-to-1 MUX, at the cost of possibly needing one inverter.
The four cases you can get are always 0, 1, C or C'.
Worked numerical 3 — building a bigger MUX from smaller ones
Build a 16-to-1 MUX using 4-to-1 MUXes only. How many are needed?
Structure: a tree.
STAGE 1 — four 4:1 MUXes, each handling 4 of the 16 inputs.
MUX1: D₀–D₃ MUX2: D₄–D₇
MUX3: D₈–D₁₁ MUX4: D₁₂–D₁₅
All four share the LOW-order selects S₁S₀.
STAGE 2 — one more 4:1 MUX selects between the four stage-1
outputs, driven by the HIGH-order selects S₃S₂.
Total: 4 + 1 = 5 four-to-one MUXes
Check the select lines: 4 needed for 16 inputs (2⁴ = 16) ✔
S₁S₀ → picks within a group
S₃S₂ → picks which group
Propagation delay = 2 MUX delays (two stages in series),
not 1 — the cost of building wide from narrow.
Where MUXes are used
🔧 Real applications
Data routingSelecting which of several sensors or registers feeds a shared bus — the classic use inside a CPU's datapath.
Parallel to serialSweep the select lines through 0,1,2,3… and the parallel inputs emerge one at a time on the single output — a serialiser.
Function generationThe universal-logic trick above. Used in FPGAs, where the basic building block is literally a small MUX-based lookup table.
Time-division multiplexingSharing one expensive channel (a phone line, an ADC) among several slower signals by sampling each in turn.
💡 Exam angle: expect "implement this function using a MUX" — a guaranteed question. Show the truth table, then the data-input assignment. The higher-mark version asks for a smaller MUX (2ⁿ⁻¹), where you pair rows and each data input becomes 0, 1, C or C'. Also remember an FPGA's LUT is a MUX — a good line to include when asked why MUXes matter.
Syllabus points
MUX operation; function implementation
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