Decoder

Digital Logic & Microprocessor — Combinational and Arithmetic Circuits, NEC licence examination syllabus (Nepal Engineering Council).

Decoders: turning a code into a single active line

Every memory chip in your computer is selected by one of these.

A decoder takes an n-bit code and activates exactly one of 2ⁿ output lines. That sounds trivial until you realise what it enables: with 16 address lines, a decoder picks one of 65,536 memory locations. Address decoding is how a processor reaches the right chip, and it's the single most practical application in this whole section.

Operation

An n-to-2ⁿ decoder: n inputs, 2ⁿ outputs, exactly ONE output active. 2-to-4 decoder equations (active HIGH): Y₀ = A'B' Y₁ = A'B Y₂ = AB' Y₃ = AB Each output is one MINTERM of the inputs. That's the key insight — a decoder generates all 2ⁿ minterms at once. Truth table: A B | Y₀ Y₁ Y₂ Y₃ ─────┼────────────── 0 0 | 1 0 0 0 0 1 | 0 1 0 0 1 0 | 0 0 1 0 1 1 | 0 0 0 1

A decoder produces every minterm simultaneously. So any function of those variables is just an OR of the right outputs — and several different functions can share one decoder. That's why a CPU has one instruction decoder feeding dozens of control lines rather than separate logic for each.

Active-low outputs, and why real chips use them

Most real decoder ICs (74138, 74139) have ACTIVE-LOW outputs: the selected line goes to 0, the rest stay at 1. Reason: memory and peripheral chips have active-low Chip Select (CS') inputs, so an active-low decoder connects directly with no inverters. To combine active-low outputs into a function, use NAND: F = (Y_a'·Y_b'·Y_c')' instead of Y_a + Y_b + Y_c

Worked numerical 1 — memory address decoding

A system has 64 KB of address space (A15–A0) and must house four 8 KB memory chips starting at 0000H. Design the decoding.

Each 8 KB chip needs how many address lines? 8 KB = 8192 = 2¹³ → 13 lines (A12–A0) go to the chip Remaining lines for chip selection: 16 − 13 = 3 lines (A15, A14, A13) → a 3-to-8 decoder (gives 8 blocks of 8 KB = 64 KB total ✔) Address ranges: A15 A14 A13 | Range | Chip ────────────┼───────────────┼────── 0 0 0 | 0000H–1FFFH | chip 0 0 0 1 | 2000H–3FFFH | chip 1 0 1 0 | 4000H–5FFFH | chip 2 0 1 1 | 6000H–7FFFH | chip 3 1 x x | 8000H–FFFFH | unused Verify chip 1's range: lowest: 001 0000000000000 = 0010 0000 0000 0000 = 2000H ✔ highest: 001 1111111111111 = 0011 1111 1111 1111 = 3FFFH ✔ size: 3FFF − 2000 + 1 = 2000H = 8192 bytes ✔ Wiring: A15,A14,A13 → decoder inputs Y₀'…Y₃' → the four chips' CS' pins A12–A0 → all four chips in parallel

Worked numerical 2 — function implementation

Implement F₁ = Σm(0,2,5,7) and F₂ = Σm(1,2,4,6) using ONE 3-to-8 decoder with active-high outputs.

A single decoder produces all eight minterms, so both functions share it: F₁ = Y₀ + Y₂ + Y₅ + Y₇ (4-input OR) F₂ = Y₁ + Y₂ + Y₄ + Y₆ (4-input OR) Note Y₂ feeds BOTH functions — decoder outputs can drive multiple gates. Cost: 1 decoder + 2 four-input OR gates. With active-LOW decoder outputs, use NAND instead: F₁ = (Y₀'·Y₂'·Y₅'·Y₇')' F₂ = (Y₁'·Y₂'·Y₄'·Y₆')' Verify F₁ at ABC = 101 (m₅): Y₅ = 1, others 0 → F₁ = 1 ✔ Verify F₂ at ABC = 101 (m₅): Y₅ not in F₂'s list → F₂ = 0 ✔

Worked numerical 3 — expanding decoders with enable

Build a 4-to-16 decoder from two 3-to-8 decoders.

Use the most significant input (D) to choose WHICH decoder is enabled, via the enable pins. Decoder 1: inputs C,B,A; enabled when D = 0 → produces outputs Y₀–Y₇ Decoder 2: inputs C,B,A; enabled when D = 1 → produces outputs Y₈–Y₁₅ Wiring for active-low enables: Decoder 1 EN' = D (active when D = 0) Decoder 2 EN' = D' (active when D = 1) → one inverter needed Trace DCBA = 1010 (decimal 10): D = 1 → decoder 2 enabled CBA = 010 → its output 2 activates Overall output = 8 + 2 = 10 ✔ Total: 2 decoders + 1 inverter. This is exactly why real decoder chips include enable pins — cascading is the main reason they exist.

💡 Exam angle: address decoding is the highest-value question here — expect 6–8 marks. The method is always the same: chip size 2ᵏ tells you k address lines go to the chip, the remaining lines feed the decoder. Show the address range table in hex and verify the boundaries. Remember real chips are active-low, so combine with NAND and connect to CS' pins.

Syllabus points

Decoder operation & design

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