Inter-processor Communication and Synchronization

Computer Organization & Embedded System — Input-Output Organization and Multiprocessor, NEC licence examination syllabus (Nepal Engineering Council).

Inter-processor Communication and Synchronization

When many processors share resources, someone has to enforce the rules.

Processors communicate either through shared memory (one writes, another reads a common location) or message passing (explicit send/receive, common in loosely-coupled systems).

Mutual exclusion and the critical section

A critical section is a piece of code that accesses a shared resource — only one process/processor should execute it at a time (mutual exclusion), or the shared data can get corrupted.

Classic race-condition example: Two processors both do: count = count + 1 (count starts at 5) Without mutual exclusion, both might read count=5 at the same time, both compute 6, both write 6 → final count = 6 (should have been 7!) This is exactly why synchronization is needed.

🚦 Semaphores and Hardware Locks

SemaphoreA shared variable used to signal availability of a resource. wait() decreases it (blocking if it hits zero), signal() increases it.

Hardware lock(like a test-and-set instruction) Provides an atomic (uninterruptible) way to check-and-claim a resource in one step — this is what makes semaphores actually safe to implement.

💡 Be ready to trace through a simple wait()/signal() sequence for two processes sharing one resource (semaphore initial value 1), showing when each process blocks or proceeds.

Why a lock needs hardware help

The obvious fix for the race condition is a flag: set it before entering the critical section, clear it after. That fails, and the reason is worth following.

while (locked == 1) /* wait */ ; locked = 1; /* claim it */ ... critical section ... locked = 0; Two processors run this simultaneously: both read locked == 0 both fall through the loop both set locked = 1 BOTH enter the critical section

The flag is itself shared data, so protecting it needs a lock — which needs a lock. The regress does not terminate in software. What breaks it is hardware: an instruction that reads and writes a memory location as one uninterruptible operation, so no other processor can act between the two halves.

🔒 What the hardware provides

Test-and-setRead the old value and write 1, atomically. If the value returned was 0 you acquired the lock; if it was 1 someone else holds it.

Compare-and-swapWrite a new value only if the current one matches what you expected — the basis of most lock-free structures.

Bus lockingHold the memory bus for the duration, so no other processor can access that address in between.

💡 "Atomic" here means indivisible, not fast. Test-and-set may take several cycles; what matters is that no other processor can observe or interfere with the intermediate state. That single guarantee is what every lock, semaphore and mutex is ultimately built on.

Spinning versus blocking

Once a lock is unavailable there are two things a processor can do, and the choice matters.

⏳ Two ways to wait

SpinLoop, retrying the lock. Wastes CPU, but responds the instant the lock frees — right when the wait will be very short.

BlockGive up the CPU and let the scheduler run something else. Costs two context switches, so it only pays when the wait is longer than that cost.

The rule follows from the numbers: spin when the expected wait is shorter than a context switch, block when it is longer. This is also why spinning is only sensible on a genuine multiprocessor — on a single CPU the lock holder cannot possibly run while you spin, so spinning guarantees you waste your entire time slice achieving nothing.

💡 Locking creates its own hazards — deadlock, and the priority inversion covered in the RTOS topic. Deadlock is treated fully in the operating-systems chapters (ACtE0704 and ACtE0705), including the four conditions and the detection and avoidance strategies.

Syllabus points

Communication mechanisms (shared memory / message passing)
Mutual exclusion, critical section
Semaphore, hardware lock
Cache coherence (brief)

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