Direct Memory Access

Computer Organization & Embedded System — Input-Output Organization and Multiprocessor, NEC licence examination syllabus (Nepal Engineering Council).

Direct Memory Access (DMA): letting hardware bypass the CPU

The busiest component in a computer doesn't need to babysit every byte.

Every time you copy a large file to a USB drive and your CPU somehow stays responsive enough to keep browsing the web at the same time, DMA is why.

The CPU only sets up the DMA controller once (start address, word count, direction), then goes off to do other work. The DMA controller directly moves data between the device and memory, interrupting the CPU only once — when the entire transfer is done.

⏱️ Cycle Stealing vs Burst Mode

Cycle stealingDMA controller "steals" one bus cycle at a time between CPU cycles, sneaking in a transfer without fully halting the CPU. Slower transfer, but CPU keeps mostly running.

Burst modeDMA takes over the bus completely for the whole block transfer in one go. Much faster block transfer, but the CPU is fully blocked from using the bus during that time.

Worked example — burst mode timing: A DMA transfer moves 2000 words. Each word takes 1 memory cycle = 200ns. Total DMA transfer time = 2000 × 200ns = 400,000ns = 400μs. During this time, in burst mode, the CPU cannot use the bus at all. In cycle stealing (say 1 in every 4 cycles given to DMA), the transfer would take roughly 4× longer in wall-clock time, but the CPU keeps running its own instructions in the other 3 of every 4 cycles.

💡 Practice this style of numerical: given transfer size, cycle time, and mode (burst/cycle-stealing), calculate total time and how much the CPU is delayed.

Syllabus points

DMA controller (block diagram, registers)
Bus request/grant; cycle stealing vs burst
DMA transfer sequence

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