Interconnection Structure

Computer Organization & Embedded System — Input-Output Organization and Multiprocessor, NEC licence examination syllabus (Nepal Engineering Council).

Interconnection Structure: how processors and memory actually wire together

More connections = more speed, but the cost grows fast.

🔀 The Five Interconnection Structures

Time-shared common busAll processors share one bus — cheap, but only one transfer happens at a time (bottleneck).

Multiport memoryMemory has a separate port for each processor — fast, but memory hardware gets complex as processor count grows.

Crossbar switchEvery processor connects to every memory module simultaneously via a grid of switches — very fast, but cost grows as n×m.

Multistage switching network(e.g. Omega network) Builds a large switch out of many small stages, reducing crosspoint cost compared to a full crossbar for large n.

HypercubeProcessors connected as corners of an n-dimensional cube — connects many processors with relatively few links per processor (each connects to log₂N others).

Crossbar switch cost numerical: A crossbar connecting n processors to m memory modules needs n × m switching points. Example: 8 processors, 4 memories → 8 × 4 = 32 crosspoints.

💡 Numerical: "How many links does each processor have in a hypercube of N=16 processors?" → log₂16 = 4 links per processor.

Syllabus points

Time-shared common bus
Multiport memory
Crossbar switch
Multistage switching network
Hypercube

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