Digital Logic & Microprocessor — Microprocessor System, NEC licence examination syllabus (Nepal Engineering Council).
Direct Memory Access: letting a device bypass the CPU
Moving a megabyte one instruction at a time is absurd. DMA moves it without the processor at all.
Consider transferring a disk sector to memory. Programmed I/O means: read a byte into the accumulator, write it to memory, increment the pointer, decrement the count, branch — five instructions per byte, and the CPU can do nothing else. DMA removes the CPU from the loop entirely: a dedicated controller takes over the buses and moves the data directly, at full bus speed.
The three transfer methods compared
🔄 Programmed I/O, interrupt-driven, and DMA
Programmed I/OCPU polls a status bit in a loop until the device is ready, then transfers. Simple, but wastes essentially all CPU time waiting. Fine for a one-off.
Interrupt-drivenThe device signals when ready, so the CPU can do other work meanwhile. Better, but still every byte passes through the CPU with interrupt overhead each time.
DMAA controller moves data directly between device and memory. The CPU is involved only twice: to set up the transfer, and to handle the completion interrupt. Orders of magnitude more efficient for blocks.
How DMA takes control
The handshake:
1. Device needs a transfer → asserts DREQ to the DMA
controller
2. DMA controller asserts HOLD (or HRQ) to the CPU
3. CPU finishes its current machine cycle, then:
· floats (tri-states) the address, data and control
buses
· asserts HLDA (Hold Acknowledge)
4. DMA controller now MASTERS the buses. It puts out the
memory address, asserts read/write, and drives DACK to
the device
5. Data moves DIRECTLY between device and memory —
never through the CPU
6. When the count reaches zero, DMA releases HOLD and
usually raises an interrupt (TC — Terminal Count)
7. CPU regains the buses and continues
Registers inside the DMA controller (per channel):
· Current Address Register
· Current Word Count Register
· Mode Register (direction, auto-init, transfer type)
DMA transfer modes
CYCLE STEALING (single transfer)
One byte per bus acquisition, then release.
CPU gets the bus back between bytes → stays responsive.
Slower overall.
BURST (block) MODE
The DMA holds the bus until the entire block is done.
Fastest transfer, but the CPU is completely stalled
meanwhile. Used for disk sectors.
DEMAND MODE
Transfers continue as long as the device keeps DREQ
asserted; pauses when it de-asserts.
TRANSPARENT (hidden) MODE
DMA only uses cycles when the CPU is not accessing
memory (e.g. during internal ALU operations).
Zero CPU slowdown, but the slowest option.
DMA is why your computer can copy a file while you keep typing. Without it, a 100 MB transfer would consume the CPU completely for its whole duration. The idea generalises: a modern GPU, network card and SSD controller are all bus masters doing their own DMA, which is why "I/O offload" is a recurring theme in computer architecture.
Worked numerical 1 — comparing transfer efficiency
Transfer 64 KB from disk to memory. Programmed I/O takes 5 instructions per byte at 2 µs each. DMA takes 1 bus cycle of 0.5 µs per byte plus 100 µs setup. Compare CPU time consumed.
Bytes to transfer = 64 KB = 65 536
PROGRAMMED I/O:
time per byte = 5 instructions × 2 µs = 10 µs
total = 65 536 × 10 µs = 655 360 µs = 0.655 seconds
CPU time consumed = 0.655 s (100% of it — the CPU IS
the transfer mechanism)
DMA (burst mode):
transfer time = 65 536 × 0.5 µs = 32 768 µs = 32.8 ms
CPU time consumed = 100 µs setup + ~50 µs interrupt
≈ 150 µs = 0.15 ms
Comparison:
wall-clock time: 655 ms vs 33 ms → 20× faster
CPU time used: 655 ms vs 0.15 ms → 4370× less
During DMA the CPU is stalled only while the bus is held
(burst mode), so with cycle stealing it could continue
executing from cache. Either way, the CPU-time saving is
what matters — that's time available for real work.
Worked numerical 2 — cycle stealing overhead
A DMA controller in cycle-stealing mode steals one bus cycle every 4 µs to transfer a byte. If a memory cycle is 0.5 µs, by what percentage is the CPU slowed?
Every 4 µs, the DMA takes 0.5 µs of bus time.
Fraction of bus time stolen:
0.5/4 = 0.125 = 12.5%
CPU slowdown ≈ 12.5% (assuming the CPU wanted the bus
continuously, which is pessimistic — real CPUs also
compute internally without bus access).
Transfer rate achieved:
1 byte per 4 µs = 250 000 bytes/second = 250 KB/s
To reach 1 MB/s we'd need one byte per 1 µs:
bus stolen = 0.5/1 = 50% → CPU halved in speed
That trade-off is exactly why burst mode exists for fast
devices: better to stall the CPU completely for 33 ms than
to halve its speed for 66 ms.
Worked numerical 3 — the 8257 DMA controller
The 8257 has 4 channels with 14-bit address and 14-bit count registers. What is the maximum block size and addressable range per channel?
Address register = 16 bits in the 8257 (14-bit count):
Count register = 14 bits → maximum 2¹⁴ = 16 384 bytes
= 16 KB per transfer
To move 64 KB you would need 4 separate DMA operations,
or a controller with a wider count register (the 8237 used
16-bit counts = 64 KB).
Channels = 4, each with independent address and count, so
four devices can have pending transfers, prioritised either
fixed (channel 0 highest) or rotating.
Setup sequence for a transfer:
1. Write the starting memory address to the channel's
address register
2. Write (byte count − 1) plus the mode bits to the
count register
3. Write the mode/control byte to enable the channel
4. Enable the device to assert DREQ
The TC (Terminal Count) output pulses when the count
reaches zero, normally wired to an interrupt input so the
CPU learns the transfer finished.
💡 Exam angle: the HOLD/HLDA handshake sequence is the core answer — list the numbered steps and emphasise that the CPU floats its buses so the DMA controller can drive them. Compare the three transfer methods with the CPU-involvement point. Know the four modes (cycle stealing, burst, demand, transparent) with their trade-offs. Efficiency numericals comparing programmed I/O with DMA are common.
Syllabus points
DMA concept; DMA controller
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