Digital Logic & Microprocessor — Microprocessor System, NEC licence examination syllabus (Nepal Engineering Council).
Memory Devices and the Hierarchy: fast, big, cheap — pick two
No single memory technology is good at everything, so computers use five at once.
Why does a computer have registers and cache and RAM and a disk, all storing bytes? Because the three things you want from memory — speed, capacity, low cost — trade against each other, and no technology gives all three. The solution is a hierarchy: a tiny amount of very fast storage at the top, huge slow storage at the bottom, and the illusion of both.
The hierarchy
t_avg = h·t_cache + (1 − h)·t_main With h = 95 %, tc = 2 ns, tmm = 100 ns, tavg = 6.9 ns.
Drop the hit rate from 99% to 95% — only four points — and watch the average time climb sharply. The misses cost fifty times more than the hits, so the last few percent of hit rate carry most of the performance.
Level Typical size Access time Cost/GB
──────────────────────────────────────────────────────
Registers 64–512 bytes 0.3 ns —
L1 cache 32–64 KB 1 ns very high
L2/L3 cache 256 KB–32 MB 3–20 ns high
Main RAM 4–64 GB 50–100 ns moderate
SSD 256 GB–4 TB 50–100 µs low
Hard disk 1–20 TB 5–10 ms very low
Tape/archive 100 TB+ seconds lowest
Note the spread: registers are about 30 MILLION times
faster than a hard disk. The hierarchy exists to hide
that gap.
Classification by volatility and writability
💾 RAM — volatile, read/write
SRAMStatic RAM. Each bit is a 6-transistor flip-flop. Fast (1–10 ns), needs no refresh, but bulky and expensive. Used for cache.
DRAMDynamic RAM. Each bit is one transistor plus one capacitor. Dense and cheap, but the capacitor leaks so it needs refreshing every few milliseconds. Used for main memory.
📀 ROM family — non-volatile
ROMMask ROM. Contents fixed during manufacture. Cheapest per unit in huge volumes, impossible to change.
PROMProgrammable once by the user, by blowing internal fuses. One shot — a mistake means a wasted chip.
EPROMErasable by ultraviolet light through a quartz window, then reprogrammable. Erase takes ~20 minutes and erases the whole chip.
EEPROMErasable electrically, byte by byte, in circuit. Slower to write and limited to ~10⁵ write cycles.
FlashLike EEPROM but erased in blocks, which makes it much faster and denser. Basis of SSDs, USB drives, phone storage.
The hierarchy only works because of locality of reference: programs tend to reuse the same data (temporal locality) and access nearby addresses (spatial locality). Without that statistical property, caching would be useless — every access would miss and you'd get disk speed with cache cost. Locality is the empirical fact that makes the whole design pay off.
Worked numerical 1 — average access time with cache
A system has 10 ns cache and 100 ns main memory with a 95% hit ratio. Find the average access time, and compare with 90% and 99%.
Average access time:
t_avg = h × t_cache + (1 − h) × t_main
At h = 0.95:
t_avg = 0.95 × 10 + 0.05 × 100
= 9.5 + 5 = 14.5 ns
At h = 0.90:
t_avg = 0.90 × 10 + 0.10 × 100 = 9 + 10 = 19 ns
At h = 0.99:
t_avg = 0.99 × 10 + 0.01 × 100 = 9.9 + 1 = 10.9 ns
Notice how sharply hit ratio matters:
90% → 19 ns
95% → 14.5 ns
99% → 10.9 ns
Improving 90%→99% nearly halves the access time. This is
why cache design obsesses over the last few percent of hit
rate. Speedup versus no cache at all:
100/14.5 = 6.9× at 95%
100/10.9 = 9.2× at 99%
Worked numerical 2 — DRAM refresh overhead
A DRAM has 4096 rows and must be fully refreshed every 64 ms. Each refresh cycle takes 100 ns. What fraction of time is lost to refresh?
Refreshes needed per 64 ms = 4096 (one per row)
Time spent refreshing:
4096 × 100 ns = 409 600 ns = 0.4096 ms
Fraction of time lost:
0.4096/64 = 0.0064 = 0.64%
So about 0.6% of memory bandwidth is consumed by refresh —
small, but non-zero, and it's pure overhead that SRAM
doesn't have.
Refresh interval per row:
64 ms / 4096 = 15.6 µs
→ one row must be refreshed roughly every 15 µs
This is why DRAM controllers are complex: they must
interleave refresh cycles with real accesses without the
CPU noticing.
Worked numerical 3 — memory chip count
Design 32 KB of memory using 8K × 4 chips. How many chips, and how are they arranged?
Required: 32 K × 8 bits
Available: 8 K × 4 bits per chip
Chips needed for WIDTH (4 bits → 8 bits):
8/4 = 2 chips side by side
Chips needed for DEPTH (8 K → 32 K):
32/8 = 4 groups
Total chips = 2 × 4 = 8 chips
Arrangement: 4 rows (banks) of 2 chips each.
Each row provides 8 K × 8
Four rows stack to 32 K × 8 ✔
Address lines:
8 K = 2¹³ → A12–A0 go to every chip (13 lines)
4 banks = 2² → A14, A13 feed a 2-to-4 decoder whose
outputs drive each bank's chip-select
Total address lines used: 15 (A14–A0) = 32 K ✔
Verify: 2¹⁵ = 32 768 = 32 K ✔
💡 Exam angle: the hierarchy diagram with typical sizes and access times is direct recall — draw it as a pyramid. The ROM family (ROM/PROM/EPROM/EEPROM/Flash) with the erase mechanism for each is a standard 4-mark question. SRAM vs DRAM comparison (transistor count, refresh, speed, use) is equally common. The average-access-time formula is a guaranteed numerical.
Syllabus points
RAM/ROM types; memory hierarchy
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