Digital Logic & Microprocessor — Microprocessor System, NEC licence examination syllabus (Nepal Engineering Council).
Synchronous and Asynchronous Transmission: who supplies the clock?
Either send a clock alongside the data, or make each byte carry its own timing.
The receiver needs to know when each bit begins. There are exactly two ways to arrange that: send a separate clock signal so both ends step together, or embed timing markers in the data itself so the receiver can synchronise on each byte. The first is faster and more efficient; the second needs no extra wire. Both are used, for different reasons.
Asynchronous transmission
No shared clock. Each CHARACTER is framed individually:
[START] [D0 D1 D2 D3 D4 D5 D6 D7] [PARITY] [STOP]
0 ← data, LSB first → opt. 1
Line idles HIGH (logic 1, called "mark")
START bit = 0 (a "space") — the falling edge tells the
receiver a character is beginning
STOP bit = 1 — guarantees a return to idle so the next
start bit produces a detectable edge
The receiver's local clock runs at 16× the bit rate. On
detecting the start edge it waits 8 ticks (half a bit) to
land in the middle of the start bit, then samples every 16
ticks thereafter — sampling each bit at its centre where
it's most stable.
Overhead: 2–3 bits per 8 data bits = 20–30%
Synchronous transmission
A common clock keeps both ends in step. Data is sent in
BLOCKS (frames), not individual characters:
[SYNC][SYNC][ ---- data, hundreds of bytes ---- ][CRC]
SYNC characters let the receiver align to the frame
No start/stop bits per character
CRC at the end checks the whole block
Clock delivery options:
· a separate clock wire (short distances)
· embedded in the data via encoding (Manchester, 8b/10b)
so the receiver recovers the clock from transitions
Overhead: a few bytes per block of hundreds → 1–5%
The 16× oversampling clock is the clever part of asynchronous reception. The receiver has no idea when a character will arrive, so it watches for the start-bit edge, then counts 8 ticks to reach the centre of that bit and confirms it's still low (rejecting noise spikes). From then on it samples every 16 ticks — always at bit centres, where the signal is most settled.
Worked numerical 1 — efficiency comparison
Compare async (8N1) and synchronous (500-byte blocks, 2 sync bytes, 2 CRC bytes) efficiency for sending 10 KB.
ASYNCHRONOUS 8N1:
10 bits sent per 8 data bits
Efficiency = 8/10 = 80%
For 10 KB = 10 240 bytes:
bits sent = 10 240 × 10 = 102 400 bits
SYNCHRONOUS (500-byte data blocks):
Blocks needed = 10 240/500 = 20.5 → 21 blocks
Per block: 2 sync + 500 data + 2 CRC = 504 bytes
Total bytes sent = 21 × 504 = 10 584 bytes
bits sent = 10 584 × 8 = 84 672 bits
Efficiency = 10 240/10 584 = 96.7%
Comparison:
async: 102 400 bits
sync: 84 672 bits
Saving = 17 728 bits = 17.3% less traffic
At 9600 bps:
async: 10.67 s
sync: 8.82 s
Synchronous wins on efficiency, which is why bulk transfer
protocols use it. Async wins on simplicity — no clock
recovery, and it tolerates arbitrary gaps between
characters, which suits a keyboard perfectly.
Worked numerical 2 — clock tolerance
In async transmission, how much can the receiver's clock differ from the transmitter's before the last bit is sampled wrongly?
The receiver samples bit n at (n + 0.5) bit-times after the
start edge. For the LAST bit (bit 9 in 8N1, the stop bit),
that's 9.5 bit times of accumulated drift.
An error becomes fatal when the sampling point drifts by
half a bit (0.5 bit-time) from the centre:
allowable drift = 0.5 / 9.5 = 5.26%
So the two clocks must agree within about ±5%.
Practical consequence: crystal oscillators (±0.01%) are
comfortably fine, but an RC oscillator (±10%) is not —
which is why microcontrollers doing serial communication
need a crystal, not just their internal RC clock.
For 11-bit frames (with parity), drift budget shrinks:
0.5/10.5 = 4.76%
This accumulated-drift limit is precisely why async
resynchronises on EVERY character: the error never gets a
chance to build up beyond one frame.
💡 Exam angle: draw the async frame with start, data, parity and stop bits labelled — that's the core diagram. Give the comparison table (overhead, clock, block size, applications) and compute efficiency for both. The 16× sampling explanation and the ±5% clock tolerance are the details that lift an answer from adequate to full marks.
Syllabus points
Sync vs async transmission
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