Digital Logic & Microprocessor — Microprocessor System, NEC licence examination syllabus (Nepal Engineering Council).
Interfacing Memory and I/O: making the processor reach the outside
Address decoding is the whole job — and getting the ranges right is the exam.
A processor has 16 address lines going nowhere in particular. Interfacing means wiring those lines so that each memory chip and each peripheral responds to its own range of addresses and stays silent otherwise. Get the decoding wrong and two chips answer at once, driving the data bus against each other — a genuine hardware fault called bus contention.
Memory-mapped versus isolated I/O
ISOLATED I/O (I/O-mapped) — what the 8085 primarily uses
Separate address spaces for memory and I/O
Distinguished by the IO/M' control signal
I/O uses only 8 address bits → 256 ports
Instructions: IN port, OUT port
Advantages: full 64 KB stays available for memory;
I/O instructions are short and fast
Disadvantage: only IN/OUT can touch I/O — you cannot
do arithmetic directly on a port
MEMORY-MAPPED I/O
Peripherals occupy addresses in the memory space
IO/M' stays low; the device looks like memory
Uses 16 address bits → up to 65 536 ports
Advantages: ALL memory instructions work on I/O
(MOV, ADD, compare — anything)
Disadvantage: consumes memory address space
The decoding methods
ABSOLUTE (full) DECODING
Every unused address line is decoded.
Each chip responds to exactly ONE address range.
More gates, but no ambiguity.
PARTIAL (linear) DECODING
Some address lines are left unconnected.
A chip responds to MULTIPLE address ranges
("foldback" or "aliasing").
Fewer gates, but wasted address space.
The universal method: a chip of size 2ᵏ takes k address lines directly, and the remaining lines must be decoded to produce its chip-select. Get k right and everything else follows. 4 KB = 2¹² so 12 lines go to the chip; with a 16-line bus, 4 lines are left to decode.
Worked numerical 1 — full memory map design
Design a system with 8 KB EPROM starting at 0000H and 8 KB RAM starting at 2000H, using absolute decoding.
Worked numerical 2 — partial decoding and foldback
A 2 KB RAM is connected with A15 as its only chip-select input (active low), leaving A14–A11 unconnected. Find all address ranges where it responds.
2 KB = 2¹¹ → A10–A0 go to the chip (11 lines)
CS' driven by A15 alone → chip responds whenever A15 = 0
Lines A14, A13, A12, A11 are IGNORED — they can be anything.
That means 2⁴ = 16 different address ranges all reach the
same 2 KB of physical memory:
0000H–07FFH (A14-A11 = 0000)
0800H–0FFFH (0001)
1000H–17FFH (0010)
1800H–1FFFH (0011)
…
7800H–7FFFH (1111)
Writing to 0000H and then reading 0800H returns the SAME
byte — the memory "folds back" 16 times.
Address space wasted: 32 KB of the map is consumed to hold
2 KB of real memory.
Trade-off: partial decoding saved a decoder chip (maybe 4
gates) at the cost of 30 KB of address space. Acceptable in
a tiny system with no expansion plans; unacceptable
otherwise.
Worked numerical 3 — I/O port interfacing
Interface an 8-bit output port at address 80H using isolated I/O, and describe the timing of an OUT 80H instruction.
Isolated I/O uses only 8 address bits (A7–A0), duplicated
on both halves of the address bus by the 8085.
Port address 80H = 1000 0000
Chip select for the port:
CS' = (IO/M' · A7 · A6' · A5' · A4' · A3' · A2' · A1' · A0' · WR')'
Practically: use an 8-bit comparator or a NAND on the
address bits, gated with IO/M' and WR'.
OUT 80H timing (10 T-states, 3 machine cycles):
M1: Opcode fetch (4 T) — reads the OUT opcode D3H
M2: Memory read (3 T) — reads the port address 80H
M3: I/O write (3 T) — IO/M' = HIGH, WR' pulses low,
data from A appears on the bus
At 3 MHz: 10 × 333 ns = 3.33 µs per OUT instruction
→ maximum output rate ≈ 300 000 bytes/second
The key distinguishing signal is IO/M':
LOW → memory access
HIGH → I/O access
Without it, the same address 0080H would clash with memory.
💡 Exam angle: this is the highest-value topic in the section — expect an 8-mark design question. The method never changes: chip size 2ᵏ → k lines to the chip, decode the rest. Always write the address range in binary AND hex, and verify the boundaries. Know the isolated-vs-memory-mapped comparison, and be ready to explain foldback if partial decoding appears.
Syllabus points
Memory & I/O interfacing
Address decoding (numerical)
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