Pipelining using VHDL

Computer Organization & Embedded System — Hardware Description Language and IC Technology, NEC licence examination syllabus (Nepal Engineering Council).

Pipelining using VHDL

Turning a slow combinational chain into a fast pipelined one — just by adding registers.

Remember the CPU pipeline from Chapter 4.1 — instructions overlapping across stages? This is the exact same idea, except now YOU are the one building the pipeline stages, in code, rather than reading about them in a CPU.

To pipeline a datapath in VHDL, you insert pipeline registers (simple D flip-flops) between combinational stages — each register holds the partial result from one stage until the next clock edge, letting multiple sets of data move through the stages simultaneously.

-- 2-stage pipelined adder-then-multiplier process(CLK) begin if rising_edge(CLK) then STAGE1_REG <= A + B; -- stage 1: add STAGE2_REG <= STAGE1_REG * C; -- stage 2: multiply (uses LAST cycle's sum) end if; end process; RESULT <= STAGE2_REG;

Notice STAGE2_REG multiplies the PREVIOUS cycle's STAGE1_REG value, not this cycle's — that one-cycle lag between stages IS the pipeline. Without the intermediate register, this would just be one big combinational expression with no overlap possible.

💡 Common question: "Modify this combinational datapath to be pipelined" — the answer is almost always "insert a register between each stage of the calculation," exactly as shown above.

What pipelining actually buys, with numbers

Take an 8 ns adder feeding a 12 ns multiplier.

UNPIPELINED — one long combinational path critical path = 8 + 12 = 20 ns maximum clock = 1/20ns = 50 MHz one result every 20 ns 2-STAGE PIPELINE — a register between the add and the multiply critical path = the SLOWEST stage = 12 ns maximum clock = 1/12ns = 83.3 MHz one result every 12 ns Throughput improves 20/12 = 1.67x Latency gets WORSE: 2 stages x 12 ns = 24 ns, against 20 ns before

Pipelining does not make any individual computation faster. It makes each one slightly slower — 24 ns instead of 20 — while allowing a new one to start every 12 ns instead of every 20. You buy throughput and you pay in latency.

Total time for N results: N unpipelined pipelined speedup 1 20 ns 24 ns 0.83x ← slower! 10 200 ns 132 ns 1.52x 100 2000 ns 1212 ns 1.65x 1000 20000 ns 12012 ns 1.67x

💡 That first row is the exam answer worth having. For a single isolated operation pipelining is a net loss. It only pays on a continuous stream, which is why processors pipeline instructions (there is always a next one) and why a pipelined design is wrong for a circuit that computes once and waits.

Why the slowest stage sets the clock

Every stage shares one clock, so the period must be long enough for the worst stage to finish. An 8 ns stage clocked at 12 ns simply idles for 4 ns of every cycle.

This is why balancing the stages matters more than adding more of them. Splitting the 12 ns multiplier into two 6 ns halves would give a 3-stage pipeline running at 8 ns — limited now by the adder. Adding stages beyond the point of balance buys nothing, because the longest stage still sets the period.

The signal rule this code depends on

The pipelined example works because of a VHDL rule that is easy to miss and fatal to get wrong.

process(CLK) begin if rising_edge(CLK) then STAGE1_REG <= A + B; STAGE2_REG <= STAGE1_REG * C; -- uses the OLD STAGE1_REG end if; end process;

Inside a process, a signal assignment does not take effect immediately — the new value appears only when the process suspends. So STAGE2_REG multiplies the value STAGE1_REG held before this clock edge, which is precisely what makes it a pipeline register rather than a wire.

💡 Rewriting these as variables (:=) destroys the pipeline. A variable updates immediately, so stage 2 would use this cycle's freshly computed sum — collapsing both stages into one long combinational path and losing every benefit while looking almost identical. This signal-versus-variable distinction is the single most common VHDL exam question, and this is why it matters.

Syllabus points

Pipeline registers between combinational stages
Pipelined datapath example

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