Overflow and Data Representation using VHDL

Computer Organization & Embedded System — Hardware Description Language and IC Technology, NEC licence examination syllabus (Nepal Engineering Council).

Overflow and Data Representation using VHDL

Choosing the right data type is half the battle in VHDL.

🧮 The Data Types You'll Actually Use

bit / std_logicA single binary value. std_logic also allows 'Z', 'U', 'X' for tri-state/unknown — much closer to real hardware behaviour than plain bit.

std_logic_vectorAn array of std_logic bits (like a bus).

integerWhole numbers, useful for counters/indices.

signed / unsigned(from numeric_std) Let you do proper arithmetic with two's complement semantics.

signal A : std_logic_vector(3 downto 0); -- a 4-bit bus signal N : integer range 0 to 15; -- a bounded integer signal S : signed(7 downto 0); -- 8-bit signed number

Detecting overflow in VHDL

When adding two signed numbers, overflow is checked exactly like in hardware: compare the sign of the operands to the sign of the result (same reasoning as in the Computer Arithmetic topic).

-- overflow if both operands have the same sign -- but the result has the opposite sign overflow <= (A(7) xnor B(7)) and (A(7) xor Sum(7));

💡 Know why std_logic is generally preferred over plain bit in real designs: it can represent unknown ('U'), high-impedance ('Z'), and don't-care states that plain bit cannot — much closer to real hardware behaviour.

The overflow this chapter is named after

Adding two 4-bit numbers can produce a 5-bit result, and VHDL will not silently widen the vector to fit.

signal A, B : unsigned(3 downto 0); -- each holds 0..15 signal SUM : unsigned(3 downto 0); SUM <= A + B; -- A=15, B=1 → 16, which needs 5 bits -- SUM gets 0000: the carry is LOST

The result is truncated to the width of the target, so 15 + 1 wraps to 0. The addition itself is correct; the destination is simply too narrow to hold the answer, and nothing warns you at run time.

🔧 The two ways to handle it

Widen the targetDeclare SUM as 5 bits and resize the operands: SUM <= resize(A,5) + resize(B,5); — no information is lost.

Capture the carryKeep SUM at 4 bits and take the fifth bit as a separate carry-out signal, which is what a hardware adder does.

💡 An n-bit adder always needs n+1 bits for a complete result. That is not a VHDL quirk but arithmetic — and it is why the ALU in ACtE0401 has a carry flag at all. The flag is that extra bit.

Signed and unsigned change what the same bits mean

The bit pattern "1111" in four bits: as unsigned → 15 as signed → −1 (two's complement) Same wires, same voltages, entirely different number.

This is why numeric_std's signed and unsigned types exist rather than doing arithmetic directly on std_logic_vector. A raw vector is just a bundle of bits with no arithmetic meaning at all — the type is what tells the tools how to interpret it, and therefore which adder to build.

💡 It also explains the carry-versus-overflow distinction from the ALU chapter: carry is the unsigned test and overflow the signed one, and which one is correct depends entirely on how the program is interpreting the bits. The hardware sets both because it cannot know.

Why std_logic rather than bit

bit holds only '0' and '1'. std_logic holds nine values, and the extra ones model things real hardware genuinely does.

⚡ The values that matter in practice

'Z'High impedance — the output is disconnected, which is how several devices share one bus without fighting.

'U'Uninitialised — a signal that has never been assigned. Seeing 'U' in simulation usually means a missing reset.

'X'Unknown or conflicting — two drivers pulling the same wire in opposite directions.

💡 These are why simulation catches bugs that bit would hide. A design that reads an uninitialised register shows 'U' propagating through the results instead of a plausible-looking 0 — the error is visible rather than silently wrong, which is the whole argument for the richer type.

Syllabus points

Data types: bit, std_logic, std_logic_vector, integer, signed/unsigned
Signed vs unsigned representation
Overflow detection in VHDL arithmetic

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