Computer Organization & Embedded System — Hardware Description Language and IC Technology, NEC licence examination syllabus (Nepal Engineering Council).
Sequential Logic in VHDL: circuits that remember
The moment you see "clock" in the question, you need a process block.
Sequential circuits need a process statement with a sensitivity list (signals that trigger the process to re-run) — almost always the clock, checked with rising_edge().
D Flip-Flop with asynchronous reset
architecture BEHAVIORAL of DFF is
begin
process(CLK, RESET)
begin
if RESET = '1' then
Q <= '0';
elsif rising_edge(CLK) then
Q <= D;
end if;
end process;
end BEHAVIORAL;
4-bit synchronous up-counter
architecture BEHAVIORAL of COUNTER4 is
signal COUNT : std_logic_vector(3 downto 0) := "0000";
begin
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
COUNT <= "0000";
else
COUNT <= COUNT + 1;
end if;
end if;
end process;
Q <= COUNT;
end BEHAVIORAL;
Simple Moore FSM skeleton
type STATE_TYPE is (S0, S1, S2);
signal STATE : STATE_TYPE := S0;
process(CLK)
begin
if rising_edge(CLK) then
case STATE is
when S0 => if X='1' then STATE <= S1; end if;
when S1 => if X='0' then STATE <= S2; else STATE <= S1; end if;
when S2 => STATE <= S0;
end case;
end if;
end process;
-- output depends only on STATE (that's what makes it Moore, not Mealy)
💡 The most commonly asked codes: D flip-flop, up/down counter, and a shift register. Practice all three from memory — the pattern (process + rising_edge + if/else) is identical every time, only the logic inside changes.
The difference between the chapter's two examples
Look carefully at where RESET is tested in the two code samples above. They are not the same circuit, and the distinction is a standard exam question.
ASYNCHRONOUS reset — the D flip-flop
process(CLK, RESET) ← RESET is in the sensitivity list
if RESET = '1' then ← checked BEFORE the clock edge
Q <= '0';
elsif rising_edge(CLK) then
Reset acts the INSTANT it is asserted, clock or no clock.
SYNCHRONOUS reset — the counter
process(CLK) ← only CLK in the sensitivity list
if rising_edge(CLK) then
if RESET = '1' then ← checked INSIDE the clock edge
COUNT <= "0000";
Reset waits for the next rising edge before taking effect.
Both are legitimate and they synthesise to different hardware. Asynchronous reset uses the flip-flop's dedicated clear pin and works even if the clock has stopped — essential for power-up initialisation. Synchronous reset is just logic on the D input, which keeps the timing analysis simpler and avoids the risk of the reset releasing too close to a clock edge.
💡 The giveaway is the sensitivity list. If RESET appears there, the reset is asynchronous; if only CLK does, it is synchronous. A question showing you a process and asking which kind of reset it implements is testing exactly that.
Why the sensitivity list matters more generally
The list names the signals that cause the process to re-evaluate. Get it wrong and simulation and synthesis disagree — which is the worst class of VHDL bug, because the design passes simulation and fails in hardware.
💡 For combinational logic in a process, every signal read must be in the sensitivity list. Omitting one means the simulator does not re-evaluate when it changes, so the old output persists — behaving like a latch in simulation, while synthesis infers real combinational logic. The two no longer describe the same circuit.
Why the counter needs an explicit width
The 4-bit counter wraps from "1111" back to "0000" automatically, because the vector cannot hold more than four bits — the carry out of the top bit is simply discarded, exactly as in the overflow topic.
💡 That wrap is usually the desired behaviour for a counter, and it is the same truncation that is a bug in an adder. Identical hardware, opposite intent — which is why VHDL will not warn you either way, and why the width must be chosen deliberately rather than inherited.