Pipelining

Computer Organization & Embedded System — Control and Central Processing Units, NEC licence examination syllabus (Nepal Engineering Council).

Pipelining: the assembly line inside your CPU

Why your CPU works like a factory, not a craftsman.

Picture a car factory. One worker builds a whole car alone — slow. Now picture an assembly line: while one car gets painted, the next already gets its engine fitted. That's pipelining — and it's the single biggest reason CPUs got dramatically faster through the 1990s and 2000s without their clock speed changing much at all.

Pipelining doesn't make one instruction faster. It overlaps many instructions in different stages at once, so more instructions finish per second overall.

Space-time diagram (4-stage instruction pipeline)

S = n·k / (k + n − 1) With k = 5, n = 10, S = 3.57 ×, eff = 71.43 %.

Raise the instruction count and the speedup climbs towards the number of stages but never reaches it — the fill and drain cost is always there. With few instructions a deep pipeline is worse than a shallow one, which is why branch mispredictions hurt so much.

Speedup formula: S = (n × tₙ) / [(k + n − 1) × t] n = number of tasks, k = number of stages, t = clock cycle time, tₙ = time for non-pipelined execution

The classic instruction pipeline has 4 stages: FI (Fetch Instruction), DA (Decode/calculate Address), FO (Fetch Operand), EX (Execute).

🚧 Hazards — when the assembly line jams

StructuralTwo stages need the same hardware at once. Fix: duplicate the resource.

DataAn instruction needs a result the previous one hasn't finished yet. Fix: forwarding, or stalling.

ControlA branch means we don't know what to fetch next. Fix: branch prediction, delayed branching.

💡 The speedup formula numerical is asked almost every year — practice plugging in n, k, t and solving for S.

Syllabus points

Concept + space-time diagram + speedup formula
Instruction pipeline (4-segment)
Arithmetic pipeline
Hazards: structural, data, control (+ handling)

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