Computer Configuration

Computer Organization & Embedded System — Control and Central Processing Units, NEC licence examination syllabus (Nepal Engineering Council).

Computer Configuration: Mano's example machine

Putting the pieces together into one working design.

To make microprogrammed control concrete, textbooks (Mano especially) walk through one complete example computer. It's a small, hypothetical machine designed purely to demonstrate how all the control-memory concepts click together — think of it as the "toy car" engineers build before designing a real one.

🗂️ The register cast

ARAddress Register — points to main memory.

PCProgram Counter — tracks the next instruction.

DRData Register — holds data being moved.

ACAccumulator — holds results.

CAR / SBRLive on the control-memory side, not the main-memory side (met in the last topic).

The key insight: this example machine has two separate memories running side by side — main memory for the program's data and instructions, and control memory for the microprograms that interpret those instructions.

You'll also see the control memory organization: it's typically organized as a fixed-width word (e.g., 20 bits) split into fields for microoperations, condition, branch, and address — and the instruction format for machine-level instructions (opcode + address field) that this microprogram is built to interpret.

💡 This topic rarely appears alone in exams — it's usually the setup paragraph before a microinstruction-format question. Understand the register names so you're not confused when a numerical references AR, DR, or AC.

Why a toy machine is worth studying

A hypothetical computer with a handful of registers can look like an academic exercise. It is the opposite: the small size is what makes the whole design visible at once.

A real processor has hundreds of instructions and pipeline stages whose interactions cannot be held in your head. The example machine has few enough that you can trace one instruction from fetch to completion and see every register that changes — which is the only way the relationship between control memory, the sequencer and the datapath becomes concrete rather than a diagram.

🗂️ What each register is for

PCWhich instruction comes next. Incremented during fetch, overwritten by a branch.

ARHolds the address currently being presented to memory — the only register wired to the address bus.

DRHolds data just read from or about to be written to memory.

ACThe accumulator, where arithmetic results land.

IRThe instruction being executed, whose opcode drives the control unit.

💡 The reason AR exists separately from PC is worth noticing: memory can only be given one address at a time, so everything that needs memory — instruction fetch, operand fetch, indirect addressing — routes through AR in turn. It is a shared resource, and the control sequence exists partly to schedule access to it.

The fetch cycle, which is always the same

Every instruction begins identically: AR ← PC put the instruction's address into AR IR ← M[AR] read that memory word into IR PC ← PC + 1 point at the next instruction Only AFTER this does the opcode in IR decide what happens, which is where the control unit branches to the right microroutine.

That fixed prefix is why microprogramming works so neatly. The fetch sequence is one shared microroutine every instruction runs before jumping to its own — so the control memory holds it once rather than repeating it in every instruction's code.

Syllabus points

Example microprogrammed computer: memory + registers (CAR, SBR, DR, AR, PC, AC)
Control memory organization + machine instruction format

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