Computer Organization & Embedded System — Control and Central Processing Units, NEC licence examination syllabus (Nepal Engineering Council).
Instruction Formats: how many addresses does an instruction need?
The architecture decision that shapes an entire instruction set.
Every instruction has an opcode (what to do) and some operand/address fields (what to do it to). But how many address fields should an instruction carry? This single design decision splits CPU architectures into different families.
Try evaluating X = (A + B) × (C + D) under each style — the number of "addresses" per instruction determines how many separate instructions you need, and how much intermediate storage they require.
🏗️ The Four Families
Three-addressADD R1, A, B — destination and both sources named directly.
Two-addressMOV R1, A; ADD R1, B — destination doubles as a source.
One-address(accumulator) LOAD A; ADD B — implicitly uses the accumulator.
Zero-address(stack) just ADD — pops two values, pushes the result.
Stack machines and RPN
Stack-based CPUs naturally compute expressions written in Reverse Polish Notation (RPN) — no parentheses needed, no precedence rules, just push operands and pop-compute-push for each operator.
💡 Guaranteed numerical: "Convert this infix expression to RPN and show the stack-machine instruction sequence." Practice at least 5 conversions until it's automatic.
The exercise, worked
Here is X = (A + B) × (C + D) written in all four styles, which is the comparison the whole topic exists to make.
THREE-ADDRESS — 3 instructions
ADD T1, A, B T1 ← A + B
ADD T2, C, D T2 ← C + D
MUL X, T1, T2 X ← T1 × T2
Shortest program, but each instruction must encode three
addresses, so the instructions themselves are long.
TWO-ADDRESS — 6 instructions
MOV T1, A T1 ← A
ADD T1, B T1 ← T1 + B (destination is also a source)
MOV T2, C
ADD T2, D
MUL T1, T2 T1 ← T1 × T2
MOV X, T1
One operand is overwritten by the result, so extra MOVs are
needed to preserve values.
ONE-ADDRESS (accumulator) — 7 instructions
LOAD A AC ← A
ADD B AC ← AC + B
STORE T1 T1 ← AC
LOAD C
ADD D
MUL T1 AC ← AC × T1
STORE X
Everything passes through one accumulator, so partial results
must be stored and reloaded.
ZERO-ADDRESS (stack) — 8 instructions
PUSH A
PUSH B
ADD pop two, push their sum
PUSH C
PUSH D
ADD
MUL pop two, push their product
POP X
The arithmetic instructions need NO address at all — operands
are implicitly the top of the stack.
The trend is the point: 3 → 6 → 7 → 8 instructions as the address count falls. Fewer addresses per instruction means shorter, simpler instructions and more of them. This is a direct trade between program length and instruction length, and neither is free.
💡 Notice the zero-address version is exactly the postfix expression A B + C D + × from the Stack Application topic. A stack machine executes postfix directly, which is why compilers convert to postfix — the conversion is not an academic exercise but the actual code-generation step.
Why modern machines are not at either extreme
Real architectures cluster around two and three addresses with a register-to-register restriction: arithmetic operates only on registers, and separate load and store instructions move data to and from memory.
The reason is that memory access dominates the cost. An instruction with three memory addresses needs three memory accesses plus the fetch; one operating on registers needs only the fetch. Restricting arithmetic to registers makes instructions fast and uniform in length, which is what makes pipelining practical — the connection to the RISC topic later in this section.