Addressing Sequencing

Computer Organization & Embedded System — Control and Central Processing Units, NEC licence examination syllabus (Nepal Engineering Council).

Address Sequencing: how the CPU finds its next micro-step

The traffic-control system inside the control unit.

We know each instruction has its own microprogram in control memory. So how does the hardware know which micro-step to run next, out of possibly hundreds sitting in that ROM? That's address sequencing — the logic that generates the address of the next control-memory word.

🧭 The three pieces that decide "what's next"

CARControl Address Register — holds the current microinstruction's address, paired with an incrementer that adds 1 to move to the next step (just like PC does for normal instructions).

MappingWhen a machine instruction like ADD is fetched, its opcode gets translated into the starting address of its OWN microroutine. This translation logic is the mapping function.

BranchingMicroprograms need jumps too — unconditional (always jump) or conditional (jump only if a status bit is set, e.g. for indirect addressing).

Common sequences like the fetch cycle get written once as a subroutine. The Subroutine Register (SBR) stores the return address, so control can jump back — just like a call stack, but in hardware.

💡 Redraw this diagram from memory in the exam: three inputs (mapping, branch, SBR) feeding a multiplexer, which loads CAR, which addresses control memory. This exact diagram is a common 5-mark question.

Syllabus points

Control Address Register (CAR) + incrementer
Mapping opcode → microroutine address
Conditional & unconditional branching
Subroutine call/return (SBR)
Address-sequencing block diagram

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