Digital Logic & Microprocessor — Interrupt Operations, NEC licence examination syllabus (Nepal Engineering Council).
Interrupt Processing and Priority: when several devices shout at once
Two interrupts arrive in the same microsecond. Something has to decide who goes first.
A single interrupt is straightforward. The interesting engineering starts when three devices raise requests simultaneously and the processor has one interrupt pin. Which is serviced first? What happens to the others? Can an urgent one interrupt a routine one already in progress? These questions have standard answers, and they show up as exam questions almost verbatim.
The interrupt cycle in detail
For a VECTORED interrupt (RST 5.5/6.5/7.5, TRAP):
1. Device asserts the interrupt line
2. CPU samples it during the LAST T-state of the current
instruction ← this is why instructions never split
3. If enabled and unmasked, the CPU:
a. sets an internal "interrupt acknowledge" state
b. executes an implicit DI
c. PUSHes the PC (2 bytes) onto the stack
d. loads the PC with the fixed vector address
4. Execution continues from the vector
5. RET pops the PC and resumes
For NON-VECTORED INTR, extra steps occur:
2b. CPU asserts INTA' (interrupt acknowledge)
2c. The DEVICE places an instruction on the data bus —
normally a RST n opcode or a CALL
2d. CPU executes that instruction, which supplies the
service address
That is why INTR needs external hardware (like the 8259)
and the others don't.
Priority resolution methods
🏁 Three ways to decide who wins
Software pollingOne interrupt line shared by all devices. The ISR reads each device's status register in a fixed order and services the first one flagged. Simple, no extra hardware, but slow — and priority is fixed by the polling order in your code.
Daisy chainingDevices are wired in a physical chain. The acknowledge signal passes from one to the next; a device that wants service blocks the signal from reaching those further down. Priority is determined by position in the chain — closest to the CPU wins. Cheap, but priority is fixed by wiring.
Priority encoder / PICA dedicated chip (the 8259) accepts up to 8 requests, resolves priority internally, and supplies the vector. Priority is programmable, and it supports masking individual channels and cascading to 64 levels.
Daisy chaining is elegant because the priority logic is the wiring itself — no gates, no programming. But it's also its weakness: to change priorities you must physically rewire the board. That's exactly the problem the 8259 solved, and why programmable interrupt controllers became universal.
Worked numerical 1 — simultaneous interrupts
RST 5.5, RST 6.5 and RST 7.5 all go active at the same instant, all unmasked. In what order are they serviced, and what are the total service times if each ISR takes 100 µs?
Priority order (highest first): 7.5 > 6.5 > 5.5
Service sequence:
t = 0 : all three pending, CPU picks RST 7.5
t = 0–100 : RST 7.5 ISR runs (others wait)
t = 100 : ISR ends with EI + RET; CPU picks RST 6.5
t = 100–200: RST 6.5 ISR runs
t = 200 : CPU picks RST 5.5
t = 200–300: RST 5.5 ISR runs
t = 300 : main program finally resumes
Waiting times:
RST 7.5: 0 µs (immediate)
RST 6.5: 100 µs
RST 5.5: 200 µs ← worst case
If TRAP had also been pending it would go FIRST, pushing
everything back by another 100 µs and giving RST 5.5 a
300 µs wait.
Design implication: put your most time-critical device on
the highest-priority input. A device that cannot tolerate a
200 µs delay must not be on RST 5.5.
Worked numerical 2 — daisy chain with three devices
Three devices are daisy-chained. Devices 2 and 3 both request service simultaneously. Trace the acknowledge signal.
Chain order: CPU → Dev1 → Dev2 → Dev3
1. Devices 2 and 3 both pull the shared INTR line low
2. CPU sees INTR, finishes its instruction, asserts INTA'
3. INTA' reaches Dev1 first
Dev1 is NOT requesting → passes INTA' through
4. INTA' reaches Dev2
Dev2 IS requesting → BLOCKS INTA' from continuing
Dev2 places its vector/RST opcode on the data bus
5. Dev3 never sees INTA' — it keeps its request asserted
6. CPU services Dev2
7. After Dev2's ISR returns and clears its request, the
still-asserted INTR causes another interrupt cycle
8. This time INTA' passes Dev1 and Dev2 (neither now
requesting) and reaches Dev3, which is serviced
Result: Dev2 first (closer to CPU), then Dev3.
Nothing is lost — Dev3's request simply persists until
served. That persistence is why level-triggered requests
work well with daisy chaining.
Worked numerical 3 — worst-case latency budget
A system has four interrupt sources with ISR durations 50, 80, 120 and 200 µs. Find the worst-case latency for the lowest-priority device, assuming no nesting.
Worst case for the lowest-priority device: all three
higher-priority interrupts arrive just before it, plus the
longest instruction must finish first.
Longest 8085 instruction: 18 T = 6 µs at 3 MHz
Wait = instruction finish + all higher ISRs
= 6 + 50 + 80 + 120
= 256 µs
Then its own ISR (200 µs) runs, so completion is at
256 + 200 = 456 µs after the request.
If the lowest-priority device is, say, a serial port
receiving at 115 200 baud, a character arrives every
86.8 µs — it would overflow long before being serviced.
Two fixes:
1. Reassign priorities — put the serial port highest
2. Enable NESTING so the serial ISR can preempt the
long 200 µs routine
Nesting analysis: with nesting allowed, the serial port's
latency becomes just 6 µs (instruction finish) + a few µs
of acknowledge, regardless of what else is running.
This is the central trade-off of interrupt design: nesting
gives low latency but risks stack overflow and re-entrancy
bugs.
💡 Exam angle: the three priority methods with advantages and disadvantages is a guaranteed 6-mark question — daisy chaining's "priority by physical position" is the phrase to use. Trace the INTA' path for the daisy chain; that's where the marks are. For the interrupt cycle, mention that the CPU samples the line in the last T-state so instructions are never split, and that INTR needs the device to supply its own vector.
Syllabus points
Interrupt cycle; priority handling
Create a free account to tick topics off, take notes as you read, watch the video lessons and get a day-by-day study plan built around your exam date.