Interrupt

Digital Logic & Microprocessor — Interrupt Operations, NEC licence examination syllabus (Nepal Engineering Council).

Interrupts: how a processor handles the unexpected

Polling a keyboard wastes millions of cycles. Interrupts let the keyboard speak up instead.

A processor executing a program has no idea a key has been pressed. It could check constantly — polling — but at 3 MHz and human typing speeds that means millions of wasted checks per keystroke. The alternative inverts the relationship: let the device interrupt the processor, forcing it to set aside what it was doing, service the event, and resume exactly where it left off. Every responsive system is built on this.

The classification

BY SOURCE Hardware interrupt — a physical signal on a pin (keyboard, timer, disk, power fail) Software interrupt — an instruction in the program (RST 0–7 on the 8085; INT n on x86) BY MASKABILITY Maskable — can be disabled by software (DI/SIM) Non-maskable — cannot be disabled; always serviced (used for catastrophic events like power failure) BY VECTORING Vectored — the interrupt has a FIXED service address built into the hardware Non-vectored — the device must supply the address on the data bus during the acknowledge cycle

The 8085's five hardware interrupts

Priority Name Vector Trigger Maskable? ────────────────────────────────────────────────────────── 1 (high) TRAP 0024H edge+level NO 2 RST 7.5 003CH rising EDGE yes 3 RST 6.5 0034H LEVEL yes 4 RST 5.5 002CH LEVEL yes 5 (low) INTR supplied LEVEL yes by device Vector address calculation for RST n: address = n × 8 RST 5.5 → 5.5 × 8 = 44 = 002CH ✔ RST 6.5 → 6.5 × 8 = 52 = 0034H ✔ RST 7.5 → 7.5 × 8 = 60 = 003CH ✔ TRAP → 4.5 × 8 = 36 = 0024H ✔ Software interrupts RST 0–7: RST 0 → 0000H RST 4 → 0020H RST 1 → 0008H RST 5 → 0028H RST 2 → 0010H RST 6 → 0030H RST 3 → 0018H RST 7 → 0038H

TRAP is non-maskable for a reason: it's wired to events you must never ignore, classically power failure. If the supply is collapsing you have milliseconds to save critical state to non-volatile memory, and a masked interrupt would lose that chance. Everything else can wait; imminent power loss cannot.

Worked numerical 1 — vector address calculation

Calculate the vector addresses for RST 3 and RST 6.5, and explain what happens if an ISR is longer than 8 bytes.

RST 3: address = 3 × 8 = 24 = 0018H RST 6.5: address = 6.5 × 8 = 52 = 0034H Note the spacing: consecutive RST vectors are only 8 bytes apart (0000, 0008, 0010, 0018 …). Eight bytes is not enough for a real ISR. So the convention is to put a JUMP at the vector address: ORG 0018H ; RST 3 vector JMP MYISR ; 3 bytes — jumps to the real handler ORG 0800H MYISR: PUSH PSW ; the actual service routine, … ; anywhere in memory POP PSW RET If you wrote a long ISR directly at 0018H, it would spill into 0020H — the RST 4 vector — and corrupt it. That's why every real 8085 program has a table of JMPs at the bottom of memory.

Worked numerical 2 — masking with SIM

Write code to enable RST 6.5 and RST 7.5 while masking RST 5.5.

SIM accumulator format for interrupt masking: bit 0 = M5.5 mask (1 = masked/disabled) bit 1 = M6.5 mask bit 2 = M7.5 mask bit 3 = MSE (Mask Set Enable — must be 1 for bits 0–2 to take effect) bit 4 = R7.5 (1 resets the RST 7.5 edge-triggered flip-flop) bit 5 = unused bit 6 = SDE (Serial Data Enable) bit 7 = SOD (Serial Output Data) We want: M5.5 = 1 (masked), M6.5 = 0, M7.5 = 0, MSE = 1 bit 3 2 1 0 = 1 0 0 1 = 09H Code: MVI A, 09H SIM ; apply the mask EI ; globally enable interrupts … Important: SIM sets the individual masks, but EI is still required — the global interrupt enable flag gates everything except TRAP. To read the current mask state, use RIM: RIM ; A now holds the mask + pending bits ANI 07H ; isolate the three mask bits

Worked numerical 3 — polling versus interrupt efficiency

A keyboard produces a character every 200 ms. Polling takes 10 instructions (20 µs) per check, done every 1 ms. An ISR takes 50 instructions (100 µs). Compare CPU overhead.

POLLING: checks per 200 ms = 200 (one per millisecond) time spent = 200 × 20 µs = 4000 µs = 4 ms overhead = 4/200 = 2% of CPU time and 199 of those 200 checks found nothing. INTERRUPT: one ISR per character = 100 µs overhead = 0.1/200 = 0.05% of CPU time Interrupt is 40× more efficient here. Now make the device faster — a character every 1 ms: polling: must check every 0.5 ms → 2000 checks/s = 2000 × 20 µs = 40 ms per second = 4% interrupt: 1000 ISRs/s × 100 µs = 100 ms/s = 10% At high event rates interrupts become MORE expensive than polling, because the fixed context-save overhead dominates. That crossover is why very high-speed devices (gigabit network cards) use DMA and polling again rather than one interrupt per packet.

💡 Exam angle: the five 8085 interrupts with priority, vector address and maskability form a table worth memorising exactly — it's direct recall. The vector formula (n × 8) is easy marks. Explain why TRAP is non-maskable, and know the SIM mask format. The 8-byte vector spacing and the JMP convention is a detail that shows real understanding.

Syllabus points

Types: hardware/software, maskable/non-maskable

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