1. IMMEDIATE — the data is in the instruction itself MVI A, 32H ; load A with the constant 32H LXI H, 2050H ; load HL with 2050H 2. REGISTER — both operands are registers MOV A, B ; copy B into A ADD C ; A = A + C 3. DIRECT — the instruction contains the memory ADDRESS LDA 2050H ; A = contents of memory 2050H STA 3000H ; memory 3000H = A 4. INDIRECT (register indirect) — a register PAIR holds the address MOV A, M ; A = contents of memory pointed to ; by HL (M means "memory at HL") LXI H,2050H MOV A,M ; A = contents of 2050H 5. IMPLIED / IMPLICIT — the operand is understood CMA ; complement A (A is implied) RAL ; rotate A left

DATA TRANSFER (no flags affected!) MOV, MVI, LDA, STA, LXI, LDAX, STAX, LHLD, SHLD, XCHG, IN, OUT, PUSH, POP ARITHMETIC (flags affected) ADD, ADI, ADC, SUB, SUI, SBB, INR, DCR, INX, DCX, DAD LOGICAL (flags affected) ANA, ANI, ORA, ORI, XRA, XRI, CMA, CMP, CPI, RLC, RRC, RAL, RAR BRANCHING JMP, JZ, JNZ, JC, JNC, JP, JM, JPE, JPO CALL, RET, and their conditional forms RST n MACHINE CONTROL HLT, NOP, EI, DI, SIM, RIM Critical exam point: DATA TRANSFER instructions do NOT affect flags. Only arithmetic and logical ones do. (Exception: INR/DCR affect all flags except CY.)

; Add ten 8-bit numbers stored from 2050H, ; store the 16-bit sum at 3000H (low) and 3001H (high) LXI H, 2050H ; HL points to the data MVI C, 0AH ; C = 10, the loop counter MVI B, 00H ; B will hold the carry/high byte XRA A ; A = 0 (also clears CY) LOOP: ADD M ; A = A + memory[HL] JNC SKIP ; if no carry, continue INR B ; carry occurred → bump high byte SKIP: INX H ; advance the pointer DCR C ; decrement the counter JNZ LOOP ; repeat until C = 0 STA 3000H ; store the low byte of the sum MOV A, B STA 3001H ; store the high byte HLT Trace with data 50H, 60H, 70H (first three): A=00, +50H → A=50H, no carry A=50H, +60H → B0H, no carry A=B0H, +70H → 1 20H → A=20H, CY=1 → B becomes 01H Running total = 0120H = 288 decimal ✔ (50H+60H+70H = 80+96+112 = 288 ✔) Why XRA A rather than MVI A,00H? XRA A is 1 byte and 4 T-states; MVI A,00H is 2 bytes and 7 T-states. XRA A also clears the carry flag, which we want.

; Find the largest of N bytes starting at 2050H ; Count N is at 2050H, data follows from 2051H ; Result stored at 3000H LXI H, 2050H ; point to the count MOV C, M ; C = count DCR C ; we'll compare N-1 times INX H ; point to the first data byte MOV A, M ; A = first number (assume largest) LOOP: INX H ; next number CMP M ; compare A with memory[HL] ; CMP does A - M but only sets flags JNC SKIP ; if A >= M, A is still the largest MOV A, M ; else the new number is larger SKIP: DCR C JNZ LOOP STA 3000H HLT The key instruction is CMP: it performs A − M internally sets CY = 1 if A < M (a borrow was needed) sets CY = 0 if A >= M sets Z = 1 if A = M but does NOT change A itself Trace with data 25H, 7FH, 40H: A = 25H CMP 7FH → 25H < 7FH → CY=1 → jump not taken → A = 7FH CMP 40H → 7FH > 40H → CY=0 → JNC taken → A stays 7FH Result: 7FH ✔ largest

; Convert a 2-digit packed BCD number in A to binary ; e.g. 45H (BCD for forty-five) → 2DH (binary 45) MOV B, A ; save the original ANI 0FH ; mask to keep the LOW nibble (units) MOV C, A ; C = units digit MOV A, B ; restore ANI F0H ; keep the HIGH nibble (tens) RRC ; rotate right 4 times to move the RRC ; tens digit into the low nibble RRC RRC ; A = tens digit MOV D, A ; save it ; now multiply tens by 10: ADD A ; A = 2 × tens ADD A ; A = 4 × tens ADD D ; A = 5 × tens ADD A ; A = 10 × tens ADD C ; A = 10×tens + units HLT Trace with A = 45H: B = 45H ANI 0FH → A = 05H, C = 05H (units = 5) A = 45H again, ANI F0H → A = 40H four RRCs → A = 04H (tens = 4), D = 04H ADD A → 08H (2×4) ADD A → 10H (4×4 = 16 decimal) ADD D → 14H (16+4 = 20 decimal = 5×4) ADD A → 28H (40 decimal = 10×4) ADD C → 2DH (40 + 5 = 45 decimal) ✔ Note the ×10 trick: 10n = ((2n × 2) + n) × 2. Four ADDs instead of a multiply loop — the 8085 has no multiply instruction, so this shift-and-add pattern is how all multiplication is done.

; Generate approximately a 1 ms delay at 3 MHz ; T-state = 333 ns DELAY: MVI C, count ; 7 T LOOP: DCR C ; 4 T JNZ LOOP ; 10 T if jump taken, 7 T if not RET ; 10 T Loop body = 4 + 10 = 14 T per iteration = 14 × 333 ns = 4.66 µs per iteration For 1 ms: count = 1000 µs / 4.66 µs = 214.6 → 215 = D7H Total time: MVI (7T) + 214 iterations × 14T + last iteration 11T + RET (10T) = 7 + 2996 + 11 + 10 = 3024 T = 3024 × 333 ns = 1.007 ms ✔ For longer delays, nest two loops: outer count × inner delay e.g. 250 × 4 ms = 1 second This is how software timing was done before hardware timers were standard — and it's why such code breaks when you change the clock frequency.