Internal Architecture and Features of Microprocessor
Digital Logic & Microprocessor — Microprocessor, NEC licence examination syllabus (Nepal Engineering Council).
Inside the 8085: what a microprocessor is actually made of
Registers, an ALU, and three buses. Everything else is detail.
Strip a microprocessor down and three things remain: places to hold numbers (registers), something to do arithmetic on them (the ALU), and wires to reach the outside world (buses). The 8085 is a good vehicle for learning this because it's small enough to understand completely while having every feature a modern CPU still has.
The register set
8-bit general purpose registers:
A (Accumulator) — one operand and the result of most
arithmetic; the most-used register
B, C, D, E, H, L — six general registers
Register PAIRS (used for 16-bit addresses):
BC, DE, HL — HL is special: it acts as a memory
pointer for many instructions
16-bit special registers:
PC (Program Counter) — address of the NEXT instruction
SP (Stack Pointer) — top of the stack in memory
Flag register (5 flags in an 8-bit register):
S — Sign (1 if result's MSB is 1, i.e. negative)
Z — Zero (1 if result is zero)
AC — Auxiliary Carry (carry from bit 3 to 4; for BCD)
P — Parity (1 if result has EVEN number of 1s)
CY — Carry (1 if carry out of the MSB)
Bit: 7 6 5 4 3 2 1 0
S Z x AC x P x CY
The three buses
ADDRESS BUS — 16 bits (A15–A0), UNIDIRECTIONAL (out only)
2¹⁶ = 65 536 addresses → 64 KB of memory space
DATA BUS — 8 bits (AD7–AD0), BIDIRECTIONAL
Carries the actual data, in or out
CONTROL BUS — individual signals, not a numbered group
RD' — read strobe
WR' — write strobe
ALE — Address Latch Enable
IO/M' — distinguishes I/O from memory access
S1,S0 — status lines
Key 8085 feature: the LOW 8 address bits SHARE pins with
the data bus (AD7–AD0 are MULTIPLEXED). ALE tells external
hardware "the address is on those pins right now — latch it"
before the pins switch to carrying data.
The multiplexed bus is the 8085's defining compromise. Intel needed 16 address lines, 8 data lines, plus control and power on a 40-pin package — it didn't fit. So the low address byte and the data share 8 pins, with ALE marking which is present. Every 8085 system therefore needs an external latch, and that's why "explain the function of ALE" is such a common exam question.
Key features of the 8085
· 8-bit data, 16-bit address (64 KB memory space)
· 3 MHz typical clock (some versions to 6 MHz)
· 6 general-purpose 8-bit registers + accumulator
· 5 flags
· 74 instruction types (246 opcodes)
· 5 hardware interrupts (TRAP, RST 7.5/6.5/5.5, INTR)
· On-chip clock generator (needs only an external crystal)
· Single +5 V supply (the 8080 needed three supplies)
· Built-in serial I/O (SID and SOD pins)
· 40-pin DIP, NMOS
· 256 I/O ports (8-bit port addresses)
Worked numerical 1 — flag behaviour after an operation
The accumulator holds 7FH. Execute ADI 01H (add immediate 1). Determine all five flags.
7FH = 0111 1111
+ 01H = 0000 0001
─────────────────
80H = 1000 0000
Flags:
S (sign) = MSB of result = 1 → S = 1 (negative if
interpreted as signed: 80H = −128)
Z (zero) = result is 80H, not 0 → Z = 0
AC (aux) = carry from bit 3 to bit 4?
1111 + 0001 in the low nibble = 1 0000
→ yes, carry out of bit 3 → AC = 1
P (parity)= count the 1s in 1000 0000 = one 1
odd → P = 0 (P is 1 for EVEN parity)
CY (carry) = carry out of bit 7? No → CY = 0
Result: A = 80H, S=1, Z=0, AC=1, P=0, CY=0
Note the AC flag: it exists purely for BCD arithmetic, where
the DAA instruction uses it to decide whether to add 6.
Worked numerical 2 — memory addressing capacity
How much memory can the 8085 address, and how many address lines would 1 MB require?
8085 address bus = 16 bits:
2¹⁶ = 65 536 bytes = 64 KB
For 1 MB = 1 048 576 bytes:
2ⁿ = 1 048 576 → n = 20 address lines
The 8085 cannot reach 1 MB directly. Options:
· BANK SWITCHING — extra latched output bits select which
64 KB bank is visible
· Use a wider processor (the 8086 has 20 lines = 1 MB)
I/O address space:
8085 uses 8-bit port addresses → 2⁸ = 256 ports
distinguished from memory by the IO/M' signal being HIGH
Total addressable: 64 KB memory + 256 I/O ports, in
separate spaces. This "isolated I/O" scheme is why IN and
OUT instructions exist as separate from MOV.
Worked numerical 3 — instruction cycle timing
The 8085 runs at 3 MHz. Find the T-state duration, and the execution time of MVI A,32H (7 T-states) and LDA 2050H (13 T-states).
Clock period (one T-state):
T = 1/3 MHz = 0.333 µs = 333 ns
MVI A,32H — 7 T-states:
time = 7 × 333 ns = 2.33 µs
LDA 2050H — 13 T-states:
time = 13 × 333 ns = 4.33 µs
Why LDA takes longer: it needs 4 machine cycles
1. Opcode fetch (4 T)
2. Memory read — low address byte (3 T)
3. Memory read — high address byte (3 T)
4. Memory read — the actual data (3 T)
Total 13 T ✔
MVI A needs only 2 machine cycles
1. Opcode fetch (4 T) 2. Memory read for the data (3 T)
Total 7 T ✔
Terminology to keep straight:
T-state = one clock period
Machine cycle = 3–6 T-states (one bus operation)
Instruction cycle = all machine cycles for one instruction
💡 Exam angle: the register list, the three buses and the five flags are all direct recall marks — write them out systematically. The two highest-value explanations are ALE and the multiplexed bus (why it exists, what the external latch does) and the T-state/machine-cycle/instruction-cycle hierarchy. Flag determination after an arithmetic operation is a very common numerical; be careful with P (even parity = 1) and AC (carry from bit 3 to 4).
Syllabus points
Registers, ALU, buses, pin diagram
Features of the microprocessor
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