Digital Logic & Microprocessor — Digital Logic, NEC licence examination syllabus (Nepal Engineering Council).
Logic Levels: turning voltages into ones and zeros
There's no such thing as exactly 5 V. Digital circuits work because they don't need it.
A "logic 1" is not a precise voltage — it's a range. This is the whole reason digital electronics is reliable while analogue is fragile. If a signal picks up 0.3 V of noise, an analogue circuit's output shifts by 0.3 V, but a digital gate still reads the same 1 and outputs a perfectly clean 1. Noise gets thrown away at every stage instead of accumulating.
The four critical voltages
On the OUTPUT side (what a gate guarantees to produce):
V_OH = minimum output voltage for logic HIGH
V_OL = maximum output voltage for logic LOW
On the INPUT side (what a gate promises to accept):
V_IH = minimum input voltage recognised as HIGH
V_IL = maximum input voltage recognised as LOW
Between V_IL and V_IH lies the FORBIDDEN / INDETERMINATE
region — an input there gives unpredictable output.
Noise margin — the reason it all works
High-level noise margin: V_NH = V_OH − V_IH
Low-level noise margin: V_NL = V_IL − V_OL
These say: how much noise can corrupt the signal before
the receiving gate misreads it?
Larger noise margin = more robust circuit.
Notice the asymmetry: a gate's output is better than its input requires (2.4 V out versus 2.0 V needed in). That gap is the noise margin, and it's deliberate. Each gate cleans up the signal it receives, so noise never accumulates through a chain of a thousand gates — which is why a CPU with billions of gates works at all.
Logic families compared
Family V_supply V_OH V_OL V_IH V_IL Margin
──────────────────────────────────────────────────────────
TTL 5 V 2.4 0.4 2.0 0.8 0.4 V
CMOS(5V) 5 V 4.4 0.5 3.5 1.5 ~0.9 V
LVCMOS 3.3 V 2.4 0.4 2.0 0.8 0.4 V
ECL −5.2 V −0.9 −1.75 −1.1 −1.5 ~0.2 V
Active LOW convention: a bar over a signal name (or a
trailing #) means the signal is ASSERTED when LOW.
Example: RESET# is active when it goes to 0 V.
Worked numerical 1 — noise margin calculation
A logic family has V_OH = 2.7 V, V_OL = 0.5 V, V_IH = 2.0 V, V_IL = 0.8 V. Find both noise margins and state which is more vulnerable.
V_NH = V_OH − V_IH = 2.7 − 2.0 = 0.7 V
V_NL = V_IL − V_OL = 0.8 − 0.5 = 0.3 V
The LOW-level margin (0.3 V) is smaller, so this family is
more vulnerable to noise on signals that are LOW.
Practical consequence: 0.3 V of ground bounce — quite
possible when many outputs switch at once — could push a
LOW input into the forbidden region and cause a false read.
That is why ground planes and decoupling capacitors matter
in real boards.
Worked numerical 2 — fan-out
A TTL gate can source 400 µA in the HIGH state and sink 16 mA in the LOW state. Each input it drives requires 40 µA (HIGH) or 1.6 mA (LOW). Find the fan-out.
Fan-out in HIGH state:
N_H = I_OH/I_IH = 400 µA/40 µA = 10
Fan-out in LOW state:
N_L = I_OL/I_IL = 16 mA/1.6 mA = 10
Fan-out = the SMALLER of the two = 10
So one output can safely drive 10 inputs. Connect an 11th
and the output voltage sags out of spec, eating into the
noise margin until the circuit becomes unreliable.
CMOS by comparison has fan-out in the hundreds, because its
insulated gate draws almost no DC input current — the limit
there is capacitive loading (which slows edges) rather than
current.
Worked numerical 3 — mixing families
Can a 3.3 V LVCMOS output (V_OH = 2.4 V) drive a 5 V CMOS input (V_IH = 3.5 V) directly?
Available HIGH from driver: 2.4 V
Required HIGH at receiver: 3.5 V
Noise margin = 2.4 − 3.5 = −1.1 V ← NEGATIVE
NO. The 5 V CMOS input would see 2.4 V, which lands in its
forbidden region (1.5 to 3.5 V). Output is unpredictable,
and the input stage may even draw excessive current with
both internal transistors partly on.
Solutions:
· a level-shifter / translator IC
· use 5 V TTL-compatible inputs instead (V_IH = 2.0 V,
which 2.4 V satisfies with 0.4 V margin ✔)
· pull-up resistor with an open-drain driver
The reverse direction (5 V out → 3.3 V in) is also unsafe:
5 V exceeds the 3.3 V part's absolute maximum and can
destroy it.
💡 Exam angle: usually a short 2–4 mark question. Define the four voltages, give the noise-margin formulas, and state the practical point — that the forbidden region must be crossed quickly and that a gate's output specification is deliberately tighter than its input requirement. Fan-out (take the smaller of the HIGH and LOW cases) appears as a one-line numerical.
Syllabus points
Logic 0/1; voltage levels
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