DSA, Database System & Operating System β Memory Management, File Systems & Administration, NEC licence examination syllabus (Nepal Engineering Council).
Memory Address
Logical versus physical addresses, and the hardware that translates between them at every single memory access.
π Where this lives: address translation is why two programs can both use address 0x1000 without colliding, and why a bug in one cannot corrupt another. It is also why malloc can return a pointer that looks like it is at 4 GB on a machine with 16 GB β the number you see is a logical address, invented for your process alone. Every segmentation fault is the MMU refusing a translation. And the same mechanism is what containers and VMs exploit: an extra translation layer means a guest can believe it owns physical memory it has never touched. Search "MMU address translation explained".
The two address spaces
LOGICAL ADDRESS (virtual address)
generated by the CPU as the program runs. What your pointer
contains. Every process has its own logical address space
starting at 0.
PHYSICAL ADDRESS
the actual address on the memory bus, seen by the RAM chips.
There is exactly one physical address space, shared by
everything.
The set of all logical addresses a process can generate is
its LOGICAL ADDRESS SPACE; the set of corresponding physical
addresses is its PHYSICAL ADDRESS SPACE.
THE MEMORY MANAGEMENT UNIT (MMU) translates one to the other,
in hardware, on EVERY access. Software translation would be
far too slow β a single instruction may touch memory three
times.
COMPILE-TIME vs LOAD-TIME vs EXECUTION-TIME BINDING:
COMPILE TIME the absolute address is fixed when compiling.
The program MUST be loaded at that address.
Used in embedded firmware with no MMU.
LOAD TIME the compiler emits relocatable code; final
addresses are fixed when the program is
loaded. Cannot move afterwards.
EXECUTION TIME binding is deferred until each access, done
by the MMU. The process CAN be moved while
running.
β this is what every general-purpose OS uses,
and it is what makes swapping and paging
possible.
THE SIMPLEST TRANSLATION β BASE AND LIMIT REGISTERS:
physical = logical + base if logical < limit
otherwise β TRAP (addressing error)
base = where the process starts in physical memory
limit = how large it is
Two registers give BOTH relocation and PROTECTION. The limit
check is the entire mechanism preventing one process from
reading another's memory, and it costs one comparison.
WORKED EXAMPLE: base = 14000, limit = 3000
logical 0 β physical 14000 β
logical 346 β physical 14346 β
logical 2999 β physical 16999 β
logical 3000 β 3000 β₯ 3000 β TRAP
logical 4000 β TRAP
Note the check is against the LOGICAL address before adding
the base β checking afterwards would allow wraparound
attacks.
READ THOSE ADDRESSES β every one is a LOGICAL address, and the
layout matches the textbook picture exactly:
0x1045b84f8 text (code) lowest
0x1045b868c rodata (string literal) just above text
0x1045c0000 data (initialised globals)
0x1045c0010 bss (uninitialised statics) β 16 bytes on
0x104d8d940 heap ~8 MB above data
0x16b846b48 stack 1.60 GB above the heap highest
THE 1.60 GB GAP is the point. Nothing occupies it. The
process's logical address space is far larger than the memory
it uses, and the gap exists so the heap can grow up and the
stack can grow down without meeting.
A machine with 16 GiB of RAM cannot have 1.6 GB of untouched
memory reserved per process β 599 processes would need a
terabyte. The gap costs NOTHING because it is only logical:
no page table entry exists for it, and no physical frame is
allocated. Touch an address in the gap and you get SIGSEGV,
because there is nothing to translate to.
heap2 β heap1 = exactly 64 bytes, so malloc placed the two
64-byte requests adjacently with no header between them
visible at this granularity.
THE SPARSE ADDRESS SPACE is the whole idea of virtual memory:
allocate address RANGES freely, commit PHYSICAL frames only
when touched. That is why a 64-bit process can mmap 1 TB of
address space on a 16 GB machine and only fail when it actually
writes too much.
The 1.60 GB gap is worth pausing on because it separates two ideas students routinely merge: address space is free, physical memory is not. Reserving address range costs a page-table entry only when a page is touched β which is why 64-bit programs can be generous with layout and why 32-bit programs, with only 4 GB of address space to spend, could not.
Fragmentation
EXTERNAL FRAGMENTATION
free memory exists but is split into pieces too small to
satisfy a request.
[used 100K][free 30K][used 200K][free 40K][used 50K]
total free = 70K, but a 50K request FAILS because no single
hole is large enough.
Β· afflicts CONTIGUOUS allocation and SEGMENTATION
Β· solved by COMPACTION (move processes to coalesce holes) β
which is only possible with execution-time binding
Β· the 50-PERCENT RULE: with first-fit, statistical analysis
shows that for N allocated blocks about 0.5N are lost to
fragmentation, i.e. up to one-third of memory wasted
INTERNAL FRAGMENTATION
memory allocated but unused, INSIDE an allocated unit.
Β· afflicts PAGING: the last page of a process is rarely full
Β· average waste = half a page per process (per segment)
MEASURED ON THIS MACHINE β page size 16 KB, not the 4 KB most
textbooks assume:
average internal fragmentation per process
= 16384 / 2 = 8192 bytes = 8 KB
across 599 processes β 4.8 MB wasted
With 4 KB pages it would be 2 KB Γ 599 β 1.2 MB. The larger
page trades more internal fragmentation for smaller page
tables β a deliberate design choice, not an accident.
ALLOCATION STRATEGIES for contiguous memory:
FIRST FIT scan from the start, take the first hole that
fits. Fastest.
BEST FIT take the SMALLEST hole that fits. Leaves tiny
unusable holes; must search the whole list.
WORST FIT take the LARGEST hole. Performs worst in practice.
NEXT FIT first fit, but resume scanning where you stopped.
EMPIRICAL RESULT: first fit and best fit both beat worst fit
on storage utilisation, and first fit is generally FASTER.
So first fit is the practical winner β best fit's extra
search buys nothing.
π Go further: modern systems add a second translation layer that the classical model does not cover. In a virtual machine, a guest's "physical" address is itself virtual to the host, so the hardware does two-level translation (Intel EPT, ARM Stage-2) β and a TLB miss can then cost a walk of two page tables. Containers avoid that entirely by sharing the host kernel and its page tables, which is a large part of why a container starts in milliseconds and a VM in seconds. Search "nested paging EPT two dimensional page walk".
π‘ Exam angle: define logical versus physical address and state that the MMU translates on every access in hardware. Know the three binding times and that execution-time binding is what permits swapping. The base and limit calculation is a standard numerical β compute the physical address and identify which logical addresses trap. Distinguish external fragmentation (free memory split into unusable holes, afflicts contiguous/segmentation, fixed by compaction) from internal fragmentation (unused space inside an allocated page, afflicts paging, averages half a page per process). Mention first-fit versus best-fit and that first fit wins in practice.
Syllabus points
Logical vs physical address; address binding
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