Pair an n-channel and a p-channel MOSFET, and current only flows when the output changes.
Start here: a million light switches left half-on
Imagine a light switch stuck exactly halfway. It is neither on nor off, and current is trickling through it continuously — so it gets warm and wastes power for nothing.
One is harmless. Now imagine a million of them in a box the size of your fingernail.
A million gates, each drawing just 1 mA continuously:
1,000,000 × 0.001 A = 1000 amps
That chip would vaporise. This is not an
exaggeration — it is why early logic families
could never have scaled to modern chip sizes.
CMOS solves this with one idea: pair the transistors so that whatever the output, one of them is always fully off. A fully-off transistor passes essentially nothing, so a resting gate consumes almost nothing.
How the pairing works
CMOS uses two complementary transistors — one that turns on with a high input, one that turns on with a low input.
🔀 Whatever the input, one is shut
Input HIGHThe lower transistor conducts and pulls the output to 0. The upper one is off, so no path exists from the supply to ground.
Input LOWThe upper transistor conducts and pulls the output to the supply. The lower one is off, so again no through path.
A million CMOS gates at rest, leaking 1 nA each:
1,000,000 × 0.000000001 A = 0.001 A = 1 mA
One thousand amps became one milliamp.
So where does the power go?
A modern processor still gets hot, which seems to contradict everything above. It does not, and the reason is the key insight of the topic.
CMOS burns power almost entirely while switching, not while resting. During the brief moment an output changes, both transistors are partly on together, and there is a short conducting path. It lasts nanoseconds — but a processor does it billions of times a second, across billions of gates.
🔥 What that explains
Faster clock, hotter chipMore switching events per second, so more power. This is why processors are throttled when hot.
Idle laptops stay coolGates that are not changing cost almost nothing, however many there are.
Lower voltage helps twiceSwitching energy depends on voltage SQUARED, so halving the supply cuts the power to a quarter — which is why chip voltages have fallen decade after decade.
💡 The exam version: CMOS static power is negligible and dynamic power dominates, proportional to frequency × capacitance × voltage². Every one of those three terms is something designers actively fight to reduce, and the squared term is why voltage reduction was pursued hardest.
Here's the problem CMOS solved. Early logic families burned power continuously — one of their transistors was always conducting, so a chip with a million gates would melt. CMOS puts a p-channel and an n-channel MOSFET in series between the supply rails and drives both gates together, arranged so that exactly one is always off. No continuous path exists from V_DD to ground, so a static CMOS gate draws essentially zero current while it's just sitting there holding a value.
The complementary pair
Complementary Metal-Oxide-Semiconductor
PMOS on top — conducts when input is LOW
NMOS below — conducts when input is HIGH
Both gates tied to the same input.
Output taken from the junction between them.
Input LOW → PMOS ON, NMOS OFF → output pulled to V_DD (HIGH)
Input HIGH → PMOS OFF, NMOS ON → output pulled to GND (LOW)
Result: a logical NOT. And at no time are both on.
Power dissipation — the whole point
Static power: P_static = V_DD × I_leakage ≈ nanowatts
(only leakage; no conducting path exists)
Dynamic power: P_dynamic = α C_L V_DD² f
α = activity factor (fraction of cycles that switch)
C_L = load capacitance
f = clock frequency
Short-circuit power: a brief pulse during the transition
when both devices are momentarily partly on.
TOTAL power is dominated by the DYNAMIC term in any active
chip — and note it scales with V_DD SQUARED.
P ∝ V_DD² is the single most consequential equation in chip design. Halving the supply voltage cuts power to a quarter at the same clock speed. Why a quarter, not a half? Because the V² term is squared. This is exactly why supply voltages fell from 5 V in the 1980s to around 1 V today. It's also why your laptop lowers both voltage and frequency when idle rather than just frequency.
✅ Why CMOS beat every rival
Near-zero static powerNanowatts when idle, versus milliwatts per gate for TTL. This alone made large-scale integration possible.
Full logic swingOutput reaches a true 0 V or a true V_DD, giving excellent noise margins.
High input impedanceAn insulated gate means one output can drive many inputs (high fan-out).
Scalable and denseShrinks well with process improvements; no resistors needed, so it packs tightly.
The costSlower than bipolar ECL, needs two transistors per input, and is vulnerable to electrostatic discharge damaging that thin gate oxide.
Worked numerical 1 — dynamic power
A CMOS chip has 2 million gates, each with 15 fF load capacitance, running at 500 MHz on a 1.2 V supply with an activity factor of 0.15. Find the dynamic power.
Total switched capacitance:
C_total = 2 × 10⁶ × 15 × 10⁻¹⁵ = 30 × 10⁻⁹ F = 30 nF
P_dynamic = α C V_DD² f
= 0.15 × 30 × 10⁻⁹ × (1.2)² × 500 × 10⁶
= 0.15 × 30 × 10⁻⁹ × 1.44 × 5 × 10⁸
= 0.15 × 21.6
= 3.24 W
Now reduce V_DD to 0.9 V (a 25% cut):
P = 0.15 × 30n × (0.9)² × 500M
= 0.15 × 30 × 10⁻⁹ × 0.81 × 5 × 10⁸
= 1.82 W
A 25% voltage reduction gave a 44% power reduction —
because of the square. This is "voltage scaling", and it
is the main lever chip designers have.
Worked numerical 2 — static vs dynamic crossover
The same chip has 50 nA leakage per gate at 1.2 V. Compare static and dynamic power at 500 MHz and at 1 kHz.
Static power (constant, independent of frequency):
I_leak_total = 2 × 10⁶ × 50 × 10⁻⁹ = 0.1 A
P_static = 1.2 × 0.1 = 0.12 W
At 500 MHz:
dynamic 3.24 W vs static 0.12 W
→ dynamic dominates (96% of total)
At 1 kHz (nearly idle):
P_dynamic = 0.15 × 30n × 1.44 × 10³ = 6.5 µW
→ static 0.12 W now dominates COMPLETELY (99.99%)
Lesson: at high speed, reduce switching. When idle, reduce
LEAKAGE — which is why modern chips power-gate whole blocks
off rather than merely slowing them down.
Worked numerical 3 — sizing for equal drive
Holes move about 2.5× slower than electrons. If the NMOS in an inverter has W/L = 2, what W/L should the PMOS have for symmetric switching?
For equal drive strength we need equal k:
k = ½μC_ox(W/L)
μ_n ≈ 2.5 μ_p
So the PMOS must be 2.5× wider to compensate:
(W/L)_PMOS = 2.5 × (W/L)_NMOS = 2.5 × 2 = 5
This is why in a real CMOS layout the PMOS transistors are
visibly LARGER than the NMOS ones — and why a CMOS gate
occupies more area than the transistor count suggests.
💡 Exam angle: a 4–6 mark question, usually "explain CMOS working with a diagram" or "why is CMOS preferred". Draw the inverter with the PMOS on top, then give the two-row truth table. Finally, state that one device is always off, so there is no static current path. That last sentence is the core mark. Then quote P = αCV²f and note the V² dependence. If asked for disadvantages, mention ESD sensitivity and lower speed than ECL.
Syllabus points
Working principle and applications
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